AlSiC (Aluminum Silicon Carbide) Packaging Substrates Procurement Guide (2026): SiC Volume Fraction Selection, Pressureless Infiltration Quality Checks and IGBT/RF Heat Sink RFQ Checklist

What You Are Actually Buying

AlSiC (Aluminum Silicon Carbide) is a metal-matrix composite (MMC): an aluminum alloy matrix infiltrated with 63–75 vol% silicon carbide particles. It is not “ceramic-coated aluminum” and not a simple Al-Si casting alloy — it is a monolithic composite formed when molten aluminum infiltrates a sintered SiC preform, most commonly via pressureless infiltration.

Three parameters define its value for power electronics:

The headline number is CTE. Alumina (DBC substrates) sits near 7 ppm/K and aluminum nitride near 4.5–5 ppm/K. AlSiC is one of very few metal-based heat sink materials that matches ceramic substrates directly, which is why soldered interfaces survive thousands of power cycles — something copper baseplates cannot claim.

Choosing the SiC Volume Fraction

Within one material family, CTE, thermal conductivity and machinability shift significantly with SiC loading. Selection is a trade-off between thermal-expansion matching and machining cost:

Rule of thumb: choose 63–68% for brazing onto alumina DBC; move to 72%+ when mating with AlN substrates or for RF parts with tight CTE budgets. High-loading grades are harder and noticeably more expensive to machine — do not pay for them without a hard CTE constraint.

Process Route Sets the Quality Floor

The mainstream route is pressureless infiltration of a SiC preform. Stir casting exists at the low end but controls porosity and particle agglomeration poorly. Buyers should know the three classic defects and their consequences:

• Residual porosity: closed pores left by incomplete infiltration. During electroless nickel plating, gas and residue inside pores expand and cause plating blisters — the number-one rejection reason for AlSiC, typically exposed only after plating, when losses are maximized.
• SiC particle agglomeration: local particle-rich zones shift CTE locally, cause edge chipping in machining and become void sources during brazing.
• Surface aluminum-rich layer: aluminum segregation at the surface late in infiltration, which hurts plating adhesion and flatness stability.

A capable supplier proves itself by running density and internal-defect inspection before plating — not by reworking blistered parts.

RFQ Checklist: 10 Items to Lock Down

1. CTE: specified over 20–100°C, test method (dilatometer) stated; demand per-batch reports, not catalog values.
2. Thermal conductivity: method (laser flash, LFA) and temperature point specified.
3. Density: ≥99.5% of theoretical (Archimedes) — the practical proxy for porosity.
4. Flatness / warpage: on DBC/AMB brazing faces, on the order of ≤0.05 mm per 100 mm; this number directly drives solder void rate.
5. Surface roughness: Ra ≤1.6 μm on solder faces as baseline; RF faces per drawing.
6. Dimensional tolerances: AlSiC is finish-machined after infiltration; ±0.05 mm on critical fits is standard — tighter needs separate pricing.
7. Plating spec: electroless Ni 3–6 μm, optionally Au 0.1–0.3 μm for solderability; include cross-hatch adhesion acceptance and a pre-plating porosity check.
8. Internal defect acceptance: ultrasonic C-scan or X-ray sampling ratio and rejection criteria written into the drawing.
9. Batch consistency: density and CTE spot-check reports per batch; multi-piece modules supplied from a single batch.
10. Cleanliness and packaging: particle-free solder faces, vacuum moisture-barrier packaging, plating shelf life stated.

2026 Reference Price Ranges (indicative only — confirm by RFQ)

Lead-time reference: tooling 3–4 weeks; first production lot 4–6 weeks. The real cost lever in AlSiC is geometry and plated area, not unit material price — removing 10% of machining area usually beats squeezing 5% off material cost. Write the pre-plating porosity check into the contract as a fixed clause; it is cheaper than any post-failure dispute.

Incoming Verification: Five Steps

1. Density sampling: Archimedes on 3–5 pcs vs theoretical; below 99.5% triggers 100% screening.
2. Dimension and flatness: CMM on brazing faces; watch for systematic warp direction — a mold-level red flag.
3. Plating checks: XRF nickel thickness, cross-hatch adhesion, 10× visual hunt for blisters.
4. Internal defects: 100% C-scan on the first lot, then sample; any agglomeration or delamination stops the line for root-cause review.
5. Property spot checks: LFA thermal conductivity and dilatometer CTE per batch, logged against lot numbers as a trend chart.

Five Ways Buyers Lose Money

1. Buying on TC alone, ignoring CTE batch spread: a glossy catalog TC with wide batch-to-batch CTE variation means solder-layer fatigue cracking in the field — warranty costs far exceed the baseplate value.
2. Flatness not on the drawing: verbal assurances fail silently; DBC brazing void rates climb and module yield drops — and the loss lands in your assembly cost center, not the supplier’s.
3. No porosity check before plating: pores are found only after nickel plating, when plating cost is already sunk. Correct practice: 100% density check pre-plating, C-scan sampling before it ever reaches the bath.
4. Benchmarking AlSiC against ordinary aluminum parts: MMC pressureless infiltration has nothing in common with die casting or extrusion. Pushing aluminum-part prices forces shortcuts exactly where porosity is controlled.
5. Ignoring tooling amortization and tiered pricing: budgeting prototypes at volume-tier unit prices, then discovering the volume pricing structure differs — and rebuilding the whole cost model.

FAQ

Q1: How do AlSiC baseplates relate to AlN substrates?
They stack, they do not compete. AlN is the ceramic insulating substrate that carries the circuit; AlSiC is the metal heat spreader beneath it. A typical IGBT module stacks copper + AlN + solder + AlSiC baseplate — AlSiC’s CTE is engineered to match exactly that stack.

Q2: Can we prototype before committing to volume? What is the MOQ?
Yes, but prototypes still carry tooling amortization. Typical MOQs run 100–500 pcs, lower for RF geometries. Order prototypes and the first production lot from the same mold to avoid a second tooling introducing batch CTE differences.

Q3: Any export-control issues with AlSiC?
Civilian power-module and RF thermal applications are generally outside dual-use control lists. Still, state end-use and end-user declarations in the contract and confirm the current HS classification and duty with your forwarder before ordering — classification interpretations occasionally differ and cause clearance delays.