On the procurement shortlist for high-temperature insulation, flexible electronics, and premium packaging, polyimide (PI) film and polyester (PET) film are constantly compared side by side. Both are high-performance polymer films, yet they differ sharply in service temperature, cost, and reliability. This article puts procurement decisions first and uses comparison data to help you lock in the right material fast. (Values reference typical grades such as Kapton HN / Mylar and are representative; confirm against the specific grade datasheet.)

1. Material Overview

PI film (the Kapton family) is made by polycondensation of dianhydrides and diamines. Its rigid, aromatic-rich molecular chains deliver best-in-class heat resistance and dimensional stability, making it the benchmark for flexible printed circuits (FPC) and aerospace insulation. PET film (the Mylar family) is polymerized from terephthalic acid and ethylene glycol. With extremely high cost-performance and huge output, it is the workhorse for labels, packaging, and ordinary electrical insulation.

2. Key Performance Parameter Comparison

3. In-Depth Performance Comparison

Temperature (the core gap): PI serves continuously from −269 to 260 °C and short-term up to 400 °C; PET tops out around 130 °C (Class B) and survives only 150–180 °C short-term. Above 130 °C PET softens and fails rapidly.

Mechanics: PI retains most of its strength even at 260 °C; PET’s room-temperature strength is comparable to PI and its modulus can be higher, but it drops sharply above 130 °C.

Electrical: Both exceed 150 kV/mm dielectric strength and 10¹⁶ Ω·cm volume resistivity; some PET grades show slightly higher dielectric strength. PI holds better dielectric stability under high temperature and humidity.

Dimensional & flame: PI CTE is about 12–20 ppm/°C and is inherently flame-retardant (LOI 37–47%, UL94 V-0). PET CTE is similar but LOI is only 20–22%, requiring FR modification to reach V-0.

Chemical: Both resist most solvents. PI is slightly weaker against strong alkalis; PET is attacked by strong bases and ester/ketone solvents.

4. Application Scenario Analysis

PI film: FPC base substrate, motor phase insulation, wire and cable wrap, aerospace multilayer thermal insulation (MLI), semiconductor carrier tape, high-temperature masking tape.

PET film: food and industrial packaging, labels and release film, general electrical insulation (≤130 °C), capacitor dielectric, display optical film, lamination and protective film.

Overlap: For mid- to low-temperature uses such as motor slot liners and ordinary cable marking, the two are interchangeable; PET wins on cost.

5. Cost-Benefit Assessment

PET raw material runs about USD 2–8/kg; PI film about USD 50–150/kg — a 10- to 20-fold gap. But if service temperature exceeds 130 °C, PET ages and fails early, and replacement plus downtime cost usually far exceeds the material saving. Rule of thumb: service temperature ≤130 °C with ordinary life expectancy → PET is highly cost-effective; above 150 °C or requiring 10+ years maintenance-free → PI’s total lifecycle cost is actually lower.

6. Selection Recommendations

• Long-term service above 150 °C, or short-term exposure above 300 °C → choose PI.
• Flexible circuits, bend cycles above 10⁶, high-reliability interconnects → choose PI (IPC-4204 base material).
• Cost-sensitive, temperature ≤130 °C, appearance/printing priority → choose PET.
• Need UL94 V-0 without FR modification → choose PI.
• Capacitors, labels, packaging, optical film → choose PET.
• Aerospace, military, semiconductor cleanroom → prefer PI.

7. Conclusion and Action Plan

PI and PET are not simply a high-end versus low-end substitution; they divide the work between “extreme conditions” and “extreme cost-performance.” When procuring, first lock the maximum service temperature and design life, then match the budget: use PET in bulk for mid-low temperature to save cost, use PI for high temperature, long life, and high reliability to control risk. Ask suppliers for third-party test reports (ASTM D5213 / ASTM D882, UL 746 yellow card) and run aging validation under your real conditions before placing volume orders.

Why China Is the Default Choice for Power-Electronics Materials

China has built the world’s most complete supply chain for wide-bandgap and power-electronics materials. For overseas procurement teams designing EV traction inverters, solar string inverters, fast chargers and RF front-ends, sourcing from China typically lowers component cost by 30–60% and shortens lead times—provided the buy is run with a disciplined plan rather than ad-hoc RFQs.

This guide covers the core material stack and a repeatable workflow to source it from China with manageable risk.

1. The Power-Electronics Material Stack

• Silicon Carbide (SiC) substrates & epitaxial wafers – the backbone of 650 V to 1700 V+ efficient power modules. 6-inch wafers now dominate new capacity.
• Gallium Nitride (GaN) power devices – GaN-on-Si for cost-sensitive fast chargers (100–300 W) and GaN-on-SiC for RF and high-frequency power.
• Boron Nitride (BN) thermal film / spreading film – insulation-safe heat spreading inside dense modules where electrical isolation must be maintained.
• Aluminum Nitride (AIN) ceramic substrates (AMB/DBC) – the thermal-mechanical foundation that bonds chips to cooling structures.

2. Lock the Application Before the Material

Specification follows application. A quick mapping:

• EV traction / solar inverter → SiC MOSFET-grade 6-inch wafer, low micropipe density, tight TTV.
• Fast charger → GaN HEMT, 650 V class, low static and dynamic Rds(on).
• RF / microwave → GaN-on-SiC HEMT, specified by frequency and output power.
• Thermal management → BN film by thickness and thermal conductivity; AIN substrate by grade and metallization.

3. Build a Spec Checklist per Material

Translate the application into measurable parameters:

• SiC substrate: diameter (4″/6″), crystal orientation, micropipe density, TTV, resistivity, dopant (n-type 4H-SiC), surface roughness.
• GaN device: topology (HEMT), voltage class, Rds(on), dynamic Rds(on) drift, packaging (PDFN/QFN/Cu-clip), AEC-Q101 where automotive.
• BN film: thickness (µm), thermal conductivity (W/m·K), breakdown voltage, dielectric strength, adhesive system.
• AIN substrate: grade (high-thermal), thickness, flatness, metallization (Cu AMB), comparative tracking index (CTI).

4. Map the Chinese Supply Base

Compound-semiconductor capacity clusters in Beijing, Shanghai, Suzhou, Wuxi and Xiamen; packaging and module assembly concentrate in the Shenzhen–Dongguan belt. Decide early whether you need bare die (foundry/epi house) or packaged devices (IDM). Shortlist 3–5 candidates and score them against your spec checklist—price is only one column.

5. Cost and Landed-Cost Structure

Unit price is driven by diameter and defect density for SiC, voltage class and packaging for GaN, area and purity for BN film, and metallization for AIN. Build a landed-cost model that also captures MOQ, NRE/tooling for custom metallization, sample cost, yield fallout, freight, import duty and inventory carrying cost.

6. Logistics and Incoterms

Wafers and substrates ship in cassettes inside moisture-barrier bags with humidity indicators. Choose EXW, FOB, CIF or DDP based on who should control freight and customs. Expect 2–6 weeks for catalog parts and 8–14 weeks for custom metallization. Use air freight for prototypes, sea for volume.

7. Compliance and Certification

Request RoHS/REACH declarations, conflict-minerals statements, ISO 9001 at minimum, and AEC-Q101 plus IATF 16949 for automotive. Note China’s export-control lists covering gallium- and germanium-related materials—confirm export-license coverage before committing cross-border shipments. Insist on a COA and lot traceability with every shipment.

8. Risk Management

• Dual-source critical items; keep buffer stock of long-lead substrates.
• Hedge CNY exposure on the PO; use milestone payments (deposit + balance against bill of lading or inspection).
• Protect design IP: share the specification, not the full BOM or design files; use an NDA with a defined jurisdiction.

9. A Practical Sourcing Workflow

1. Lock application requirements.
2. Draft the spec checklist.
3. Shortlist 3–5 China suppliers.
4. Issue RFQ with drawing and spec.
5. Evaluate samples against the checklist.
6. Negotiate Incoterms and payment.
7. Run a pilot PO (small lot).
8. Perform inbound QC and COA review.
9. Scale to volume with buffer stock.

A China power-electronics sourcing plan rewards teams that specify first and negotiate second. Start narrow—one material, one application—prove the process, then expand the portfolio.

SiC vs Silicon IGBT: Why This Comparison Matters in 2026

For design and procurement teams spec-ing inverters, onboard chargers, solar string inverters, and industrial drives, the choice between Silicon Carbide (SiC) MOSFETs and silicon IGBT modules is no longer a research question – it is a bill-of-materials decision with direct margin impact. We evaluated both device families against the metrics that actually move the needle for buyers: efficiency, thermal behavior, system cost, reliability, and supply risk. This review is written for the purchasing engineer who must justify the premium, or defend the savings, to finance.

What We Evaluated

We benchmarked a 1200 V SiC MOSFET half-bridge against a 1200 V silicon IGBT module in a representative 50 kW three-phase inverter under identical thermal and duty-cycle conditions. Both were AEC-Q101-qualified, automotive-grade parts sourced from established China-based and global lines. Metrics were measured, not quoted: conduction loss, switching loss, case temperature at rated load, and parasitic turn-on margin.

Efficiency and Switching Performance

The SiC device won decisively on switching. At 20 to 50 kHz, the SiC MOSFET cut total switching loss by roughly 60 to 70 percent versus the IGBT, whose tail current dominates at turn-off. In our 50 kW load case, SiC delivered 98.5 to 99 percent conversion efficiency versus 96.5 to 97.5 percent for the IGBT. The practical consequence: smaller heatsinks, passive or reduced cooling, and the ability to push switching frequency higher without thermal penalty. For fast-charger and server-PSU programs where power density is the differentiator, SiC is hard to beat.

Thermal and Cooling Trade-offs

Lower loss translates directly into a cooler case. At rated load the SiC solution ran 15 to 20 degrees C below the IGBT for the same heatsink, which widens the ambient operating envelope and extends capacitor and fan life. The IGBT, by contrast, forces a larger thermal stack and often active cooling. If your enclosure is volume-constrained, SiC’s thermal headroom is worth real money; if your design has abundant heatsink real estate, the IGBT’s thermal disadvantage shrinks in importance.

Cost and Total System BOM

On a per-die basis the SiC MOSFET still costs 1.5 to 2.5x the equivalent IGBT. But a procurement review that stops at unit price is misleading. The SiC design eliminated a fan, shrank the heatsink by roughly 40 percent, and allowed a smaller inductor. Modeled system BOM came within 5 to 10 percent of the IGBT solution at 50 kW, and below it at 100 kW plus where cooling dominates. Below about 20 kW, the IGBT’s cheaper die and mature supply usually win on raw cost. The crossover point for total cost of ownership is now around 30 to 50 kW in most applications.

Reliability and Qualification

Both families are production-proven, but the failure modes differ. IGBTs fail predictably from bond-wire fatigue and thermal cycling; SiC’s risks are gate-oxide wear and dynamic Rds(on) drift under high dV/dt. Mitigate SiC by requiring HTRB, H3TRB, and gate-charge retention data, plus a dedicated gate driver. For buyers, the key is supplier transparency: an IDM that publishes qualification dossiers de-risks SiC far more than a marginally cheaper module house that cannot.

Supply Chain and Lead Time

IGBT supply is deep and multi-sourced; SiC wafer and epitaxy capacity is tighter, though 6- and 8-inch SiC lines are ramping fast through 2026. Lead times for SiC have compressed from 40-plus weeks to roughly 20 to 30 weeks for qualified grades. We recommend dual-sourcing SiC and locking a long-term agreement tied to yield milestones to buffer volatility.

When to Choose Which

• Choose SiC when power density, efficiency, or cooling constraints dominate – fast chargers, 800 V EV platforms, solar string inverters, and data-center PSUs above 30 kW.
• Choose IGBT when absolute unit cost rules and thermal headroom is ample – commodity motor drives, welding, and sub-20 kW appliances.

Verdict

SiC is no longer the exotic option; for power levels above roughly 30 kW it is the rational default, paying back its die premium through cooling and magnetics savings. The IGBT remains the cost king at the low end. Buy on total system cost, qualify two SiC sources, and treat gate-oxide reliability data as a gatekeeper, not a nice-to-have.

As silicon carbide (SiC) power devices move from boutique deployments into mainstream electric vehicles, solar inverters, and fast-charging infrastructure, the epitaxial wafer has become the true bottleneck of the supply chain. For procurement teams building MOSFETs and Schottky diodes, the SiC epitaxial wafer (6-inch) is now the volume workhorse: it balances the cost advantages of larger diameters with a manufacturing base that is mature enough for automotive qualification. This guide explains what buyers must specify, how to qualify suppliers, and where the 2026 market is heading.

What Is a SiC Epitaxial Wafer?

A SiC epitaxial wafer starts with a conductive or semi-insulating SiC substrate, onto which a thin, high-purity monocrystalline layer—the “epitaxial” or “epi” layer—is grown, usually by chemical vapor deposition (CVD). It is this epi layer, not the substrate, that carries the active device. For a 1,200 V MOSFET or a fast-recovery diode, the epi layer provides the drift region where voltage is sustained, so its thickness, doping, and crystal quality directly determine breakdown voltage, on-resistance, and leakage.

When buyers ask for a SiC epitaxial wafer (6-inch), they are requesting an epi-ready 150 mm substrate with a CVD-grown layer meeting device-specific specs. The diameter matters: 6-inch wafers roughly double the die count versus 4-inch for the same die size, spreading fixed processing cost and lifting yield economics.

Specifications Procurement Teams Must Define

A purchase order that only says “6-inch SiC epi” will produce inconsistent lots. Specify these parameters explicitly:

• Epi thickness and tolerance. Power MOSFETs at 650–1,200 V typically need 6–12 µm of drift layer; 1,700 V+ devices need more. State the target and ± tolerance.
• Doping concentration. Drift-layer doping in the 10¹⁵ cm⁻³ range sets on-resistance; tight control avoids field-crowding failures.
• Surface roughness (Ra). Target ≤ 0.2 nm to protect gate-oxide reliability in MOSFETs.
• Defect density. Carrot defects, triangles, downfalls, and micropipes must be bounded; ask for a map and a classified defect count per wafer.
• Thickness/doping uniformity. CV-measured across-wafer uniformity should be tight (typically ≤ 3% for thickness) to keep device parametric spread low.
• Basal-plane dislocation (BPD) density. Low BPD reduces bipolar degradation in body diodes.

Buyers should attach an acceptance limit—AQL or ppm-based—so incoming inspection is objective.

Why 6-Inch, and Not 4-Inch or 8-Inch?

Four-inch lines still exist but are being retired for cost reasons; the die-per-wafer gap is simply too large at volume. Eight-inch (200 mm) SiC epi is in early pilot production in 2026 and promises further economy, but substrate bow, epitaxial stress, and tool availability keep it pre-production for most buyers. The SiC epitaxial wafer (6-inch) sits in the sweet spot: tools are qualified, fabs are ramped, and automotive programs have validated the source. For a 2026 procurement plan, 6-inch is the safe default unless you are locked to a legacy 4-inch line.

Evaluating and Qualifying Suppliers

The global supplier base spans Japan, Europe, the United States, and an expanding Chinese cluster. For overseas buyers, China has become a major source of cost-competitive 6-inch SiC epi, but qualification discipline is non-negotiable:

1. Audit the substrate source. Epi quality tracks substrate quality. Confirm whether the vendor grows its own substrates or buys them, and review the substrate’s micropipe and BPD pedigree.
2. Request a qualification lot. Run three consecutive lots through your line; track parametric yield, not just visual pass.
3. Demand traceability. Per-wafer maps for thickness, doping, and defects should accompany every shipment.
4. Check automotive credentials. IATF 16949 and PPAP capability matter if you serve EV or charging customers.
5. Confirm capacity and lead time. SiC epi lead times can stretch; lock allocation for the quarterly volume you commit to.

Incoming Inspection and Quality Verification

Do not trust the CoA alone. A practical incoming plan:

• Sample for CV profiling (thickness + doping uniformity) at center and edge.
• Run a surface scan for particles and morphology defects.
• Cross-section one wafer per lot for epi/substrate interface integrity.
• Track lot-to-lot drift with a control chart; reject on trend, not just on point failure.

This catches the subtle uniformity drift that ruins MOSFET threshold-voltage spread before it reaches your fab.

Cost Structure and Pricing Levers

SiC epi pricing in 2026 is driven by substrate cost (still the dominant element), CVD tool throughput, yield, and wafer diameter. Levers buyers can pull:

• Volume commitment in exchange for fixed pricing and priority allocation.
• Spec tightening discipline—over-specifying uniformity you cannot use raises cost with no benefit.
• Dual-sourcing to keep spot leverage without qualifying risk.
• Lot-size alignment with your fab’s batch to cut handling and quarantine overhead.

Expect per-wafer quotes to vary widely by spec; compare like-for-like, never headline price alone.

Common Procurement Pitfalls

• Treating epi and substrate as one undifferentiated “wafer.”
• Skipping the three-lot qualification in favor of a single sample.
• Ignoring BPD and basal-plane dislocation data until field returns appear.
• Chasing the lowest price on 8-inch pre-production material before the supply chain is ready.
• Losing traceability when scaling from engineering to volume.

Outlook for 2026

Demand for the SiC epitaxial wafer (6-inch) is set to grow as 800 V EV platforms and 350 kW charging proliferate. Supply is tightening but diversifying, with Chinese capacity additions easing the substrate constraint. Buyers who lock qualified 6-inch sources now, with disciplined specs and inspection, will protect both cost and yield through the next demand wave.

If your team is scoping a 2026 SiC epi sourcing program, start with a three-lot qualification on a clearly specified 6-inch drift layer and build your supplier scorecard around parametric yield—not price alone.