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  • Substrato de Carboneto de Silício (SiC): Guia de Compras para Wafers de Grau Eletrónico de Potência da China

    Por que o Substrato de Carboneto de Silício (SiC) é o gargalo que importa

    Cada dispositivo de potência em carboneto de silício começa numa monocristal. Antes da camada epitaxial, do MOSFET ou de um inversor de tração de 1200 V, há o substrato 4H-SiC — a wafer monocristalina que suporta todo o dispositivo. À medida que os inversores de tração de veículos elétricos, os carregadores ultrarrápidos de 800 V, os inversores de string fotovoltaicos, o armazenamento à escala da rede e os acionamentos de motores industriais migram dos IGBTs de silício para os MOSFETs SiC, o substrato tornou-se o nó da cadeia de abastecimento que mais limita diretamente o rendimento, o custo e a entrega.

    A China opera hoje a maior capacidade instalada mundial de crescimento de cristais SiC e processamento de substratos, abrangendo o crescimento de bolacha por transporte de vapor físico (PVT), corte, retificação, polimento e epitaxia. Para as equipas de aprovisionamento que procuram escala competitiva em custo, a China é a região de aprovisionamento por defeito para substratos SiC — desde que saiba escrever uma especificação que os fornecedores cumpram. Este guia apresenta os parâmetros, as vias de fornecimento e a disciplina de qualificação que separam uma wafer com rendimento em produção de uma que destrói silenciosamente os dies.

    Substrato vs. Wafer Epitaxial: não confunda os dois

    Um erro frequente do comprador é tratar “wafer SiC” como um só produto. São dois:

    • Substrato: a wafer monocristalina 4H-SiC polida que fornece a base da rede cristalina. Este é o tema deste guia.
    • Wafer epitaxial: um substrato com uma camada 4H-SiC de grau dispositivo crescida por CVD por cima. É uma compra separada com a sua própria especificação.

    Comprar bem o substrato é um pré-requisito para comprar bem a epi. Especifique e qualifique-os como itens de linha distintos.

    Defina a classe do dispositivo antes da wafer

    A classe de tensão do dispositivo alvo orienta tanto a qualidade do substrato como a epi que mais tarde empilhará:

    • Classe 650 V: carregadores embarcados, fontes de servidor, acionamentos industriais — mais tolerante no orçamento de defeitos.
    • Classe 1200 V: inversores principais de VE e carregamento rápido de 800 V — o motor de volume em 2026, exige contagens de dislocação de plano basal (BPD) muito baixas.
    • Classe 1700 V+: ferroviário, rede e indústria pesada — camadas de deriva espessas, substratos mais estritos.

    Confirme com a engenharia a classe do dispositivo alvo e a topologia antes de emitir qualquer pedido de cotação. A especificação de substrato necessária para um MOSFET de 1200 V não é a necessária para um interruptor RF.

    A sua tabela de especificação RFQ: o que deve constar na ordem de compra

    Especificações vagas são a causa nº 1 de material de entrada rejeitado. Fixe estes parâmetros com o certificado de análise (COA) do fornecedor antes de encomendar:

    Parâmetro Especifique Gama típica 2026
    Diâmetro 150 mm (6 polegadas) corrente; 200 mm (8 polegadas) em rampa 150,0 ± 0,2 mm
    Polítipo / orientação 4H-SiC, 4° fora do eixo (0001) para <11-20> —
    Resistividade n-tipo (baixa ρ) para deriva MOSFET; semi-isolante (alta ρ) para RF n-tipo 0,015–0,025 Ω·cm; SI > 1e5 Ω·cm
    Densidade de microtúbulos Alvo zero microtúbulos 0 cm⁻² (máx. 0,1)
    BPD / TSD / TED BPD baixo crítico para rendimento bipolar BPD < 200 cm⁻²; TSD < 500 cm⁻²; TED < 2000 cm⁻²
    Espessura Combinar com manuseio e plano de epi 350–500 µm (6 polegadas)
    Rugosidade superficial (Ra) Acabamento CMP, medido por AFM < 0,5 nm
    TTV / bow / warp Apertado para uniformidade de epi TTV < 5 µm; bow < 15 µm
    Exclusão de borda Definir área útil 3–5 mm
    Referência do lado frontal Entalhe ou borda plana, marca de orientação Por desenho
    Embalagem Cassete por wafer, anti-ESD Purga N₂, barreira de humidade

    Especifique, não confie em promessas

    Avalie o próprio produto. Um regime de entrada orientado por especificação protege o rendimento melhor do que qualquer credencial em papel:

    • Exija um COA com mapas. Insista em mapas de resistividade por wafer, mapas de espessura e mapas de dislocação — não números de ponto único.
    • Execute inspeção de entrada. Use XRD para polítipo e orientação, Raman ou UV para qualidade cristalina, AFM para rugosidade, e ataque KOH mais microscopia ótica para dislocações. Uma pequena verificação de metrologia de terceiros no primeiro lote paga-se a si própria.
    • Qualifique por lote de amostra. Alimente lotes pela sua linha ou por um laboratório e correlacione a densidade de defeitos do substrato com o rendimento final do dispositivo antes de aumentar o volume.
    • Escreva os limites de aceitação no contrato. Estabeleça no PO o máximo admissível de BPD, microtúbulos e TTV para que as disputas sejam quantificáveis.

    Vias de fornecimento: grower de bolacha, casa de substratos ou integrado?

    A cadeia de substratos SiC da China oferece três vias:

    1. Casas de substratos integradas: crescem a bolacha e acabam a wafer numa só linha; ideais para programas de grande volume e design fixo com um único responsável pela qualidade.
    2. Growers de bolacha dedicados que abastecem fábricas de substratos: flexíveis em volume mas exigem controlo de entrada mais forte na fase de corte/polimento.
    3. IDM / fabricantes de módulos que compram substratos: adequados a clientes verticalmente integrados que acabam a epi e os dispositivos internamente.

    Para compradores no estrangeiro, uma casa de substratos com histórico de exportação comprovado e uma segunda fonte redundante reduz o risco de prazo e geopolítico. Confirme cedo a postura de controlo de exportação e duplo uso; substratos semi-isolantes de grau RF recebem mais escrutínio de licenciamento do que os n-tipo de grau potência.

    Estrutura de custos e alavancas de negociação

    O custo do substrato é governado pelo rendimento da bolacha — o crescimento de cristal PVT é o gargalo — mais corte, retificação e polimento, e finalmente pelo seu orçamento de defeitos. A rampa de 200 mm (8 polegadas) está a baixar o custo por centímetro quadrado, mas wafers de 8 polegadas de baixo defeito ainda têm prémio. Use estas alavancas:

    • Compromisso de volume para garantir preço de buffer.
    • Qualificação multi-fonte para evitar dependência de um único fornecedor.
    • Acordo de longo prazo (LTA) ligado a marcos de rendimento.
    • Consignação ou inventário gerido pelo fornecedor para procura estável.

    Modele o custo total de posse: uma wafer barata com BPD alto pode anular a poupança em devoluções em campo. Preço por wafer é a métrica errada; preço por die bom é a certa.

    Logística, embalagem e documentos

    • Embalagem: cassete por wafer, blindagem anti-ESD, purga N₂, dessecante dentro de saco de barreira de humidade. Vibração e estática são os dois assassinos em trânsito.
    • Código HS: wafers SiC de grau semicondutor costumam cair em HS 3818.00 (preparações para dispositivos semicondutores) ou 8541.90 (partes de dispositivos semicondutores). Confirme o código exato com o seu despachante para o país de importação.
    • Prazo: substratos qualificados de 6 polegadas tipicamente demoram 8–16 semanas; especificações mais estritas estendem-no. Planeie o reabastecimento em conformidade.
    • Incoterms e documentos: comum FOB Xangai ou Shekou; solicite fatura comercial, lista de embalagem, certificado de origem e COA em cada envio.

    Cinco armadilhas que custam aos compradores

    • Tratar o grau do substrato como igual à especificação da epi. Um bom substrato pode ainda crescer uma epi má; qualifique cada um separadamente.
    • Aceitar BPD alto. As dislocações de plano basal geram falhas de empilhamento em dispositivos bipolares e destroem o rendimento.
    • Ignorar TTV e bow. Quebram a uniformidade de epi e o manuseio da wafer na ferramenta.
    • Saltar mapas de PL/ataque de entrada. O que não mede, não gere.
    • Subestimar prazo e risco ESD. Ambos param a sua linha.

    Lista de verificação RFQ (pronta a copiar)

    Item Confirme antes de encomendar
    Diâmetro e orientação 150 mm, 4H-SiC, 4° fora do eixo
    Resistividade e tipo n-tipo (potência) ou SI (RF)
    Limites de defeito (contratuais) BPD, microtúbulos, TSD/TED máximos
    Rugosidade, TTV, bow Ra < 0,5 nm; TTV < 5 µm
    COA com mapas resistividade, espessura, dislocação por wafer
    Qualificação por lote de amostra correlação de rendimento acordada
    Embalagem e prazo cassete N₂, 8–16 semanas
    Código HS e documentos confirmado com despachante

    Perspetiva de mercado 2026

    Com a rampa de linhas de 200 mm e a escalagem da capacidade de substratos da China, 2026 é o ano em que o custo por wafer de substrato SiC cai enquanto a disponibilidade alarga — mas o material de 8 polegadas de baixo defeito mantém-se apertado e com prémio. Os compradores que hoje fecham acordos de dupla fonte e disciplinam a inspeção de entrada absorverão o pico de procura de VE e carregamento de 800 V sem erosão de margem.

    Conclusão

    Aprovisionar um substrato de carboneto de silício (SiC) é menos sobre encontrar a wafer polida mais barata e mais sobre desriscar a fundação de todo o seu dispositivo. Defina a classe do dispositivo, fixe a especificação, qualifique duas fontes por lote de amostra e negoceie pelo custo por die bom. As equipas que constroem esta disciplina hoje liderarão a próxima vaga de concursos de VE, carregamento rápido e fotovoltaico.

    LiiFoo ajuda compradores no estrangeiro a construir um processo de aprovisionamento na China orientado por especificação para substratos SiC — da especificação RFQ e qualificação por lote de amostra à revisão de COA, inspeção de entrada e logística completa. Peça uma cotação e fixe a especificação de substrato certa para o seu programa de 2026.

  • 碳化硅（SiC）衬底采购指南：海外买家如何从中国选型功率电子级晶圆

    为什么碳化硅（SiC）衬底是关键瓶颈

    每一颗碳化硅功率器件都始于一块单晶。在生长外延层、制造 MOSFET、打造 1200 V 主驱逆变器之前，先有这片4H-SiC 衬底—承载整颗器件的单晶晶圆。随着电动汽车主驱逆变器、800 V 超充、光伏组串逆变器、电网级储能与工业电机驱动从硅基 IGBT 大规模转向 SiC MOSFET，衬底已成为直接限制良率、成本与交期的关键供应链节点。

    中国目前已建成全球最大的 SiC 晶体生长与衬底加工产能，覆盖物理气相传输（PVT）长晶、切割、研磨、抛光与外延全链条。对追求成本优势的规模化项目而言，中国是 SiC 衬底的默认采购区域—前提是你写得出供应商真正能兑现的规格。本指南梳理了参数、采购路径与认证纪律，帮助你区分”量产稳定良率”与”悄悄吞噬裸片”的晶圆。

    衬底与外延片：切勿混为一谈

    买家常犯的一个错误，是把”SiC 晶圆”当作单一产品。其实它分两种：

    • 衬底：抛光单晶 4H-SiC 晶圆，提供晶格基础。本指南的主题。
    • 外延片：在衬底上通过 CVD 生长器件级 4H-SiC 层。属于另一项独立采购，有独立规格。

    把衬底买好，是买好外延片的前提。请将两者作为独立行项目分别指定与认证。

    先定器件等级，再定晶圆

    目标器件的电压等级，决定了衬底质量以及后续外延的规格：

    • 650 V 等级：车载充电机、服务器电源、工业驱动—对缺陷预算最宽容。
    • 1200 V 等级：电动汽车主逆变器与 800 V 超充—2026 年的放量主力，对基面位错（BPD）数量要求极严。
    • 1700 V+ 等级：轨道交通、电网与重工业—漂移层厚，对衬底最严苛。

    发出任何询价前，请与设计团队确认目标器件等级与拓扑。为 1200 V MOSFET 所需的衬底规格，与射频开关所需并不相同。

    你的 RFQ 规格表：必须写进采购订单的内容

    规格模糊是来料被拒的首要原因。请在下单前与供应商的分析证书（COA）中锁定以下参数：

    参数 指定要求 2026年常见范围
    直径 150 mm（6英寸）主流；200 mm（8英寸）放量中 150.0 ± 0.2 mm
    晶型/取向 4H-SiC，偏轴4°（0001）朝<11-20> —
    电阻率 n型（低阻）用于MOSFET漂移区；半绝缘（高阻）用于射频 n型 0.015–0.025 Ω·cm；SI > 1e5 Ω·cm
    微管密度 零微管目标 0 cm⁻²（最高0.1）
    BPD/TSD/TED 低BPD对双极器件良率至关重要 BPD < 200 cm⁻²；TSD < 500 cm⁻²；TED < 2000 cm⁻²
    厚度 匹配加工与外延计划 350–500 µm（6英寸）
    表面粗糙度（Ra） CMP后，AFM测试 < 0.5 nm
    TTV/弯曲/翘曲 严格以保证外延均匀性 TTV < 5 µm；弯曲 < 15 µm
    边缘排除区 定义有效面积 3–5 mm
    正面基准 notch或平边，取向标记 按图纸
    包装 单片刻盒，防静电 充氮、防潮屏障

    用规格评估，而非用承诺评估

    评估请聚焦产品本身。以规格驱动、严谨的来料管控，比任何纸面资质都更能保障良率：

    • 索要带图谱的COA。坚持要求晶圆级电阻率图、厚度图与位错图，而非单点数值。
    • 执行来料检验。用 XRD 查晶型与取向，拉曼或 UV 查晶体质量，AFM 测粗糙度，KOH 腐蚀加光学显微镜查位错。首批次做一次小型第三方计量验证，回报远超成本。
    • 以样品批次做准入。将批次送入自有产线或测试机构，关联衬底缺陷密度与最终器件良率，再决定是否放量。
    • 将验收上限写入合同。在 PO 中明确 BPD、微管与 TTV 的最大允许值，使争议可量化。

    采购路径：长晶厂、衬底厂还是一体化？

    中国的 SiC 衬底链条提供三条路径：

    1. 一体化衬底厂：从长晶到抛光同线完成；适合设计锁定、大批量项目，质量责任单一。
    2. 专业长晶厂供应衬底加工线：批量灵活，但在切割/抛光环节需更强来料管控。
    3. IDM/模块厂外购衬底：适合自行完成外延与器件制造的纵向整合客户。

    对海外买家而言，选择具备出口记录且设有冗余第二源的衬底厂，可降低交期与地缘风险。请尽早确认出口管制与两用物项立场；射频级半绝缘衬底比功率级 n 型受到更多许可审查。

    成本结构与议价杠杆

    衬底成本由长晶良率主导—PVT 晶体生长是瓶颈—加上切割、研磨、抛光，最后由你的缺陷预算决定。200 mm（8 英寸）放量正拉低每平方厘米成本，但低缺陷的 8 英寸晶圆仍有溢价。可运用以下杠杆：

    • 以批量承诺换取缓冲报价。
    • 多源认证，避免单一供应商绑定。
    • 与良率里程碑挂钩的长期协议（LTA）。
    • 对稳定需求采用寄售或供应商管理库存。

    请核算总拥有成本：高 BPD 的廉价晶圆，可能因现场返修抵消其节省。每片价格是错误的指标，每颗良裸片成本才是对的。

    物流、包装与单证

    • 包装：单片刻盒、防静电屏蔽、充氮、配干燥剂并置于防潮袋中。震动与静电是运输中的两大杀手。
    • HS编码：半导体级SiC晶圆通常归入HS 3818.00（半导体用制备品）或8541.90（半导体器件零件）。请与报关行确认进口国的准确税号。
    • 交期：合格6英寸衬底通常8–16周；规格越严交期越长，请据此规划补货。
    • 贸易术语与单证：常见FOB上海/蛇口；每批发货请索取商业发票、装箱单、原产地证及COA。

    让买家吃亏的五个坑

    • 把衬底等级等同于外延规格。好衬底也可能长出差的外延层，请分别认证。
    • 接受高BPD。基面位错会在双极器件中诱发层错，直接摧毁良率。
    • 忽视TTV与弯曲。它们破坏外延均匀性与设备上的晶圆传送。
    • 跳过来料PL/腐蚀图谱。无法度量就无法管理。
    • 低估交期与静电风险。两者都会导致产线停线。

    RFQ清单（可直接复制）

    项目 下单前确认
    直径与取向 150 mm，4H-SiC，偏轴4°
    电阻率与类型 n型（功率）或SI（射频）
    缺陷上限（合同化） BPD、微管、TSD/TED最大数量
    粗糙度、TTV、弯曲 Ra < 0.5 nm；TTV < 5 µm
    带图谱的COA 逐片电阻率、厚度、位错
    样品批次准入 已约定良率关联
    包装与交期 充氮盒，8–16周
    HS编码与单证 已与报关行确认

    2026 年市场展望

    随着 200 mm 产线放量、中国衬底产能爬坡，2026 年将是 SiC 衬底每片成本下降、供给扩大的年份—但低缺陷的 8 英寸材料仍紧俏并享有溢价。当下锁定双源协议、严抓来料检验的买家，将能在电动汽车与 800 V 超充需求激增时稳住毛利。

    结论

    采购一片碳化硅（SiC）衬底，关键不在于找到最便宜的抛光晶圆，而在于为你整颗器件的地基去风险。明确器件等级、锁定规格、以样品批次认证双源、按每颗良裸片成本议价。今天建立这套纪律的团队，将引领下一波电动汽车、超充与光伏招标。

    来芙 LiiFoo 帮助海外买家建立以规格驱动的中国 SiC 衬底采购流程—从 RFQ 规格表、样品批次准入，到 COA 评审、来料检验协同与全程物流。获取报价，为你的 2026 年项目锁定最合适的衬底规格。

  • Silicon Carbide (SiC) Substrate Procurement: How Overseas Buyers Source Power-Electronics-Grade Wafers from China

    Why Silicon Carbide (SiC) Substrates Are the Bottleneck That Matters

    Every silicon carbide power device begins with a single crystal. Before there is an epitaxial layer, a MOSFET, or a 1200 V traction inverter, there is the 4H-SiC substrate — the monocrystalline wafer that carries the entire device. As electric-vehicle traction inverters, 800 V ultra-fast chargers, photovoltaic string inverters, grid-scale storage, and industrial motor drives migrate from silicon IGBTs to SiC MOSFETs, the substrate has become the supply-chain node that most directly limits yield, cost, and delivery.

    China now operates the world’s largest installed capacity for SiC crystal growth and substrate processing, spanning physical vapor transport (PVT) boule growth, slicing, grinding, polishing, and epitaxy. For procurement teams chasing cost-competitive scale, China is the default sourcing region for SiC substrates — provided you can write a specification that suppliers actually meet. This guide lays out the parameters, sourcing routes, and qualification discipline that separate a wafer that yields in production from one that quietly destroys die.

    Substrate vs. Epitaxial Wafer: Do Not Conflate the Two

    A frequent buyer error is treating “SiC wafer” as one product. It is two:

    • Substrate: the polished monocrystalline 4H-SiC wafer that provides the lattice foundation. This is the subject of this guide.
    • Epitaxial wafer: a substrate with a CVD-grown device-grade 4H-SiC layer on top. It is a separate purchase with its own specification.

    Buying the substrate well is a prerequisite for buying the epi well. Specify and qualify them as distinct line items.

    Define the Device Class Before the Wafer

    The voltage rating of your target device drives both substrate quality and the epitaxy you will later stack on it:

    • 650 V class: onboard chargers, server PSUs, industrial drives — most forgiving on defect budget.
    • 1200 V class: EV main inverters and 800 V fast charging — the volume driver in 2026, demands very low basal-plane dislocation (BPD) counts.
    • 1700 V+ class: rail, grid, and heavy industrial — thick drift layers, strictest substrates.

    Confirm the target device class and topology with your design team before issuing any request for quotation. The substrate spec you need for a 1200 V MOSFET is not the one you need for an RF switch.

    Your RFQ Specification Table: What Must Appear in the Purchase Order

    Vague specifications are the number-one cause of rejected incoming material. Pin these parameters down with the supplier’s certificate of analysis (COA) before you order:

    Parameter Specify Typical 2026 range
    Diameter 150 mm (6 inch) mainstream; 200 mm (8 inch) ramping 150.0 ± 0.2 mm
    Polytype / orientation 4H-SiC, 4° off-axis (0001) toward <11-20> —
    Resistivity n-type (low ρ) for MOSFET drift; semi-insulating (high ρ) for RF n-type 0.015–0.025 Ω·cm; SI > 1e5 Ω·cm
    Micropipe density Zero-micropipe target 0 cm⁻² (max 0.1)
    BPD / TSD / TED Low BPD critical for bipolar yield BPD < 200 cm⁻²; TSD < 500 cm⁻²; TED < 2000 cm⁻²
    Thickness Match handling & epitaxy plan 350–500 µm (6 inch)
    Surface roughness (Ra) CMP-finished, AFM measured < 0.5 nm
    TTV / bow / warp Tight for epitaxy uniformity TTV < 5 µm; bow < 15 µm
    Edge exclusion Define usable area 3–5 mm
    Front-side reference Notch or flat, orientation mark Per drawing
    Packaging Single-wafer cassette, ESD-safe N₂ purge, moisture barrier

    Specify, Do Not Trust Promises

    Evaluate the product itself. A spec-driven, disciplined incoming regime protects yield better than any paper credential:

    • Require a COA with maps. Insist on wafer-level resistivity maps, thickness maps, and dislocation maps — not single-point numbers.
    • Run incoming inspection. Use XRD for polytype and orientation, Raman or UV for crystal quality, AFM for roughness, and KOH etching plus optical microscopy for dislocations. A small third-party metrology check on the first lot pays for itself.
    • Qualify by sample lot. Feed lots through your own line or a test house and correlate substrate defect density with final device yield before you ramp volume.
    • Write acceptance limits into the contract. State maximum allowable BPD, micropipe, and TTV in the PO so disputes are quantifiable.

    Sourcing Routes: Boule Grower, Substrate House, or Integrated?

    China’s SiC substrate chain offers three routes:

    1. Integrated substrate houses: grow the boule and finish the wafer in one line; best for design-locked, high-volume programs with a single accountable quality owner.
    2. Dedicated boule growers feeding substrate fabs: flexible on volume but demand stronger incoming control at the slicing/polish stage.
    3. IDM / module makers buying substrates: suited to vertically integrated customers who finish epi and devices themselves.

    For overseas buyers, a substrate house with a proven export record and a redundant second source reduces lead-time and geopolitical risk. Confirm export-control and dual-use posture early; RF-grade semi-insulating substrates get more licensing scrutiny than power-grade n-type.

    Cost Structure and Negotiation Levers

    The substrate’s cost is governed by boule yield — PVT crystal growth is the bottleneck — plus slicing, grinding, and polishing, and finally by your defect budget. The 200 mm (8 inch) ramp is bringing down cost per square centimeter, but low-defect 8-inch wafers still carry a premium. Use these levers:

    • Volume commit to secure buffer pricing.
    • Multi-source qualification to avoid single-supplier dependency.
    • A long-term agreement (LTA) tied to yield milestones.
    • Consignment or vendor-managed inventory for steady demand.

    Model total cost of ownership: a cheaper wafer with high BPD can erase its savings through field returns. Price per wafer is the wrong metric; price per good die is the right one.

    Logistics, Packaging, and Documents

    • Packaging: single-wafer cassette, ESD shielding, N₂ purge, desiccant inside a moisture-barrier bag. Vibration and static are the two killers in transit.
    • HS code: semiconductor-grade SiC wafers usually fall under HS 3818.00 (preparations for semiconductor devices) or 8541.90 (parts of semiconductor devices). Confirm the exact code with your broker for the import country.
    • Lead time: qualified 6-inch substrates typically run 8–16 weeks; tighter specs extend it. Plan replenishment accordingly.
    • Incoterms & documents: commonly FOB Shanghai or Shekou; request a commercial invoice, packing list, certificate of origin, and COA with every shipment.

    Five Pitfalls That Cost Buyers

    • Treating substrate grade as equal to epi spec. A good substrate can still grow a poor epi layer; qualify each separately.
    • Accepting high BPD. Basal-plane dislocations seed stacking faults in bipolar devices and wreck yield.
    • Ignoring TTV and bow. They break epitaxy uniformity and wafer handling on the tool.
    • Skipping incoming PL/etch maps. What you cannot measure, you cannot manage.
    • Underestimating lead time and ESD risk. Both stop your line.

    RFQ Checklist (Copy-Ready)

    Item Confirm before ordering
    Diameter & orientation 150 mm, 4H-SiC, 4° off-axis
    Resistivity & type n-type (power) or SI (RF)
    Defect limits (contractual) BPD, micropipe, TSD/TED maxima
    Roughness, TTV, bow Ra < 0.5 nm; TTV < 5 µm
    Mapped COA per-wafer resistivity, thickness, dislocation
    Sample-lot qualification yield correlation agreed
    Packaging & lead time N₂ cassette, 8–16 weeks
    HS code & documents confirmed with broker

    2026 Market Outlook

    With 200 mm lines ramping and China’s substrate capacity scaling, 2026 is the year SiC substrate cost per wafer falls while availability widens — but low-defect 8-inch material remains tight and commands a premium. Buyers who lock dual-source agreements and discipline their incoming inspection now will absorb the EV and 800 V charging demand surge without margin erosion.

    Conclusion

    Procuring a silicon carbide (SiC) substrate is less about finding the cheapest polished wafer and more about de-risking the foundation of your whole device. Define the device class, lock the specification, qualify two sources by sample lot, and negotiate on cost per good die. Teams that build this discipline today will lead the next wave of EV, fast-charging, and photovoltaic tenders.

    LiiFoo helps overseas buyers build a spec-driven China sourcing process for SiC substrates — from RFQ specification and sample-lot qualification to COA review, incoming inspection, and full logistics. Request a quote and lock the right substrate spec for your 2026 program.

  • Product Review: Boron Nitride Thermal Film – Evaluating Thermal Spreading Films for Power-Module Management

    Introduction: Why Boron Nitride Thermal Film Matters Now

    As silicon-carbide and gallium-nitride power modules push switching frequencies and current densities ever higher, heat has become the dominant limit on reliability. Conventional thermal-interface materials (TIMs) such as silicone greases and graphite sheets struggle to spread localized hot spots across large substrates. Boron nitride (BN) thermal film-a flexible, electrically insulating sheet built around hexagonal BN fillers-has emerged as a leading solution for power-module thermal management. This review evaluates its performance, specifications, and procurement considerations for engineering and sourcing teams.

    What Is Boron Nitride Thermal Film?

    BN thermal film is a thin, conformable sheet produced by aligning hexagonal boron nitride (h-BN) platelets inside a polymer or non-woven carrier. h-BN delivers a rare combination: high in-plane thermal conductivity (commonly 15 to 60 W/m K), excellent electrical insulation (dielectric strength typically above 10 kV/mm), and intrinsic chemical inertness. The outcome is a film that spreads heat laterally away from hot components while never conducting current-a property that is critical in high-voltage power electronics.

    Why It Outperforms Conventional TIMs

    Silicone greases and phase-change pads conduct heat primarily through thickness and can pump out or dry over time. Graphite sheets conduct well but are electrically conductive and prone to causing shorts. BN film avoids both failure modes: its oriented platelets provide strong in-plane spreading, and the ceramic fillers remain fully dielectric. For power modules, that translates into lower junction temperatures, a more uniform temperature map, and longer lifetime under repeated thermal cycling.

    Key Specifications to Check in an RFQ

    • In-plane vs through-plane conductivity: vendors usually quote both; in-plane spreading is what relieves hot spots.
    • Thickness and conformability: films of 0.1 to 0.5 mm balance contact resistance against mechanical compliance.
    • Dielectric strength: confirm above 10 kV/mm to maintain isolation under high bias.
    • Operating temperature: quality films sustain 200 to 300 C without delamination.
    • Thermal resistance (R theta): request measured C cm2/W rather than only raw conductivity.
    • Carrier type: non-woven, silicone-free, or PI-based, chosen by outgassing limits.

    Application Fit: Where BN Film Wins

    BN thermal film is best suited to IGBT and SiC power modules, automotive traction inverters, onboard chargers, and datacenter power supplies where hot-spot mitigation drives reliability. It is less cost-effective for low-power consumer devices that can use cheaper graphite or silicone pads. Specify it when electrical isolation and lateral heat spreading must coexist in the same interface.

    Handling and Installation Notes

    BN film is mechanically more delicate than metal-backed solutions. Avoid sharp bending and keep contact surfaces clean before lamination. Because the material is non-tacky by default, some grades ship with a light adhesive or require a clamping frame to hold contact pressure. Confirm the recommended pressure (often 0.5 to 2 MPa) with your assembly process to prevent air gaps that inflate thermal resistance. These practical details are frequently overlooked yet directly affect measured performance.

    Procurement and Quality Considerations

    Source from suppliers that provide third-party thermal and dielectric test reports rather than datasheet claims alone. Request sample lots and run your own thermal-impedance measurement. Verify silicone-free grades where outgassing matters for the enclosure. For automotive programs, confirm relevant reliability and material declarations. Multi-source qualification protects against single-supplier lead-time risk as demand scales through 2026.

    Cost and Market Outlook

    BN film costs more per square meter than graphite or silicone TIMs, but the system-level savings-smaller heat sinks, higher power density, fewer field failures-often justify the premium. With SiC adoption accelerating in electric vehicles and renewables, demand for high-performance thermal spreading films is climbing. Buyers who lock dual-source agreements now will absorb supply swings more smoothly.

    Verdict

    Boron nitride thermal film is a mature, high-value material for power-module thermal management where isolation and hot-spot spreading are non-negotiable. Pin down in-plane conductivity and dielectric strength in your RFQ, qualify two sources, and validate with sample thermal testing. For high-voltage power electronics, it ranks among the most dependable thermal-interface choices available today.

  • 2026中国锂电材料出口态势：产能格局、合规要点与全球供应链

    出口基本面

    中国已稳居全球锂电材料供应链核心，正极、负极、电解液、隔膜四大主材均具备显著产能与成本优势。2026年，海外电芯与储能厂商对中国材料的依赖度持续高位，出口品类由基础材料向高镍正极、硅碳负极、新型电解液添加剂延伸。

    主要出口材料与采购关注

    • 正极材料： 高镍三元与磷酸铁锂（LFP）并行，海外储能偏好LFP，动力电池侧重高镍。
    • 负极材料： 人造石墨为主，硅负极渗透率提升，采购需关注比表面积与首效。
    • 电解液与添加剂： 六氟磷酸锂（LiPF6）及新型锂盐供应链集中，需评估批次稳定性。
    • 隔膜： 湿法涂覆隔膜为主，关注孔径一致性与热收缩率。

    合规与物流要点

    锂电材料多属非危化品，但部分前驱体、添加剂涉及出口管制与MSDS、REACH、TSCA等合规文件。海外买家应提前确认HS编码、原产地证明与运输资质，并要求供应商提供稳定的第三方检测报告。

    供应链建议

    建议分散多源采购、锁定长协价以对冲锂盐价格波动，并在下单前完成样品级电性能验证。对中小买家而言，通过具备出口资质的贸易商或产业平台集中采购，可降低合规与最小起订量门槛。

  • Solid-State Battery Materials Roadmap 2026: Electrolytes, Cathodes and the Path to Scale-Up

    The Shift Beyond Liquid Electrolytes

    Solid-state batteries replace the flammable liquid electrolyte with a solid ion conductor, promising higher energy density, improved safety, and longer cycle life. The material stack—solid electrolyte, cathode, anode—is where the real engineering and supply-chain opportunity lies.

    Solid Electrolyte Chemistries

    • Sulfide electrolytes (e.g., Li10GeP2S12, argyrodites): highest ionic conductivity, but moisture-sensitive and requiring controlled dry-room processing.
    • Oxide electrolytes (LLZO, LATP): chemically stable and air-tolerant, but brittle and needing high-temperature sintering.
    • Polymer electrolytes: flexible and easy to manufacture, yet limited by lower room-temperature conductivity.

    Cathode and Anode Choices

    High-nickel layered oxides and lithium cobalt oxide remain common cathodes; lithium-metal anodes are the target for maximum energy density, though dendrite control is critical. Sulfide-based routes currently lead pilot lines, while oxide approaches suit premium niche applications.

    Scale-Up Challenges for Buyers

    Cost, dry-room capex, interfacial resistance, and inconsistent pilot yields are the main gating factors. Procurement teams should track electrolyte powder suppliers, sulfide precursor availability, and coating/stacking equipment readiness before committing volume contracts.

  • Why PFA Leads Ultra-Pure Fluoropolymer Tubing for Semiconductor Manufacturing

    What Is PFA and Why Fabs Rely on It

    PFA (perfluoroalkoxy alkane) is a fully fluorinated, melt-processable fluoropolymer that combines the chemical inertness of PTFE with the fabrication flexibility of thermoplastics. In semiconductor front-end and wet-processing lines, where even trace metallic ions can ruin a wafer, PFA’s ultra-low extractables and smooth, non-stick surface make it the default choice for fluid handling.

    Key Properties for Semiconductor-Grade Use

    • Ultra-high purity: Total metallic extractables typically below ppb levels; meets SEMI F57 guidelines for chemical distribution systems.
    • Chemical resistance: Stable against aggressive acids and solvents (HF, H2SO4, HNO3, bases) used in cleaning and etching.
    • Temperature range: Continuous service from -200 °C to ~260 °C.
    • Low surface energy: Minimizes particle adhesion and secondary contamination.

    Typical Applications

    PFA is used for chemical delivery tubing, valve diaphragms, pump components, wafer carriers, and PFA-lined tanks. In wet benches and CMP slurry lines, PFA piping protects yield by keeping ionic and particulate contamination in check.

    Sourcing Considerations for Overseas Buyers

    When qualifying PFA components, verify resin grade (virgin vs. repurposed), lot-level purity certification, and compatibility with your chemical matrix. Leading supply comes from Japan, the US, and increasingly China; request SEMI F57 test reports and confirm whether the product is PFA or a lower-grade FEP/ETFE substitute.

  • 2026-09-07 Price Trend Daily Report

    This report monitors price trends of five key advanced materials: PTFE resin, PEEK resin, carbon fiber, PI film, and specialty ceramic raw materials. Overall, high-end electronic materials remain firm on AI-server, HBM and low-altitude-economy demand, bulk fluoropolymers consolidate at highs, carbon fiber is bottoming and rebounding, and specialty ceramic raw materials are edging up mildly.

    Price Overview

    Material Current Price Range Weekly Change Trend
    PTFE Resin (Susp. Medium) ¥32,000–34,000/ton +1% Firm-Stable
    PEEK Resin (Domestic Std.) ¥300,000–400,000/ton +1% Slight Up
    Carbon Fiber (T300/T700) ¥80–150/kg +1% Bottom Reversal
    PI Film (Std./High-End) ¥240,000–3,000,000/ton 0%~+0.5% High-End Strong
    Specialty Ceramic Raw Mats. ¥2,700–300/kg +0.5% Mild Rise

    Key Movements

    • PTFE Resin: +1% (Consolidating at highs after a ~30% surge in July; fluorspar/HF-acid cost support persists, and the industry’s “output control & price protection” discipline stays firm)
    • Carbon Fiber: +1% (Bottom reversal confirmed. Toray’s Jan +10–20% hike and Jilin Chemical Fiber follow-through, plus low-altitude-economy eVTOL demand, with inventories falling from highs)
    • High-End PI Film: Firm (Kaneka raised all PI film prices 20% in April; AI-server/Rubin and HBM demand lock the high-end electronic-grade supply deficit through 2027)

    Impact Analysis

    • Procurement Cost: PTFE at a relative high pressures anti-corrosion/sealing costs — lock 2–3 months of inventory. Carbon fiber at historic lows benefits wind-blade and aero-composite buyers. High-end PI film is costly — place orders 3 months ahead.
    • Supply Chain: PTFE fluorspar tightness extends supplier lead times; carbon fiber’s ~86% localization boosts autonomy; high-end PI/PEEK remain import-dependent — watch FX and geopolitical logistics risk.

    Action Recommendations

    • Lock In Now: PTFE resin (cost-push, hard to fall — lock 2–3 months immediately), High-end PI film (supply deficit — pre-stock)
    • Hold & Watch: Carbon fiber (rebound but high inventory — buy in batches), PEEK industrial grade (domestic capacity caps price — JIT), Specialty ceramic raw materials (ample supply — JIT)

  • 2026-09-07 价格趋势日报

    本报告监控PTFE树脂、PEEK树脂、碳纤维、PI薄膜及特种陶瓷原料五大关键新材料的价格走势。整体看，高端电子材料受AI服务器、HBM及低空经济拉动维持偏强，大宗氟聚合物高位盘整，碳纤维底部企稳回升，特种陶瓷原料平稳微涨。

    价格概览表

    材料 当前价格区间 周环比 趋势
    PTFE树脂（悬浮中粒） 3.2–3.4万元/吨 +1% 稳定偏强
    PEEK树脂（国产标准级） 30–40万元/吨 +1% 稳中有升
    碳纤维（T300/T700） 80–150元/千克 +1% 企稳回升
    PI薄膜（常规/高端） 24–300万元/吨 0%~+0.5% 高端偏强
    特种陶瓷原料（氧化铝/氮化硅） 2700–300元/千克 +0.5% 平稳微涨

    重点变动

    • PTFE树脂：+1%（高位盘整。7月暴涨约30%后于高位企稳，萤石、氢氟酸等上游成本支撑仍在，行业”控量保价”挺价意愿强）
    • 碳纤维：+1%（底部反转确认。日本东丽1月起提价10%–20%、吉林化纤跟涨，低空经济eVTOL需求拉动，行业库存自高位回落）
    • PI薄膜高端：偏强（钟渊化学4月全系列提价20%；AI服务器/Rubin架构、HBM需求致高端电子级供给缺口锁定至2027年）

    影响分析

    • 对采购成本：PTFE处历史相对高位，化工防腐密封件成本承压，建议锁定2–3个月库存；碳纤维处历史低位，风电叶片与航空航天复材采购成本利好；PI高端膜成本高企，需提前3个月下单。
    • 对供应链：PTFE萤石供应偏紧、供应商交期延长；碳纤维国产化率约86%提升供应链自主性；PI/PEEK高端牌号仍依赖进口，需关注汇率与地缘物流风险。

    行动建议

    • 建议锁定：PTFE树脂（成本推动、易涨难跌，立即锁2–3月）、PI高端膜（供给缺口、提前备货）
    • 建议观望：碳纤维（底部反弹但库存仍高，可分批择机）、PEEK工业级（国产扩产压制价格，按需采购）、特种陶瓷原料（供应充足，保持即时采购）

  • 2026-09-07 Price Trend Daily Report

    This report monitors price trends of five key advanced materials: PTFE resin, PEEK resin, carbon fiber, PI film, and specialty ceramic raw materials. Overall, high-end electronic materials remain firm on AI-server, HBM and low-altitude-economy demand, bulk fluoropolymers consolidate at highs, carbon fiber is bottoming and rebounding, and specialty ceramic raw materials are edging up mildly.

    Price Overview

    Material Current Price Range Weekly Change Trend
    PTFE Resin (Susp. Medium) ¥32,000–34,000/ton +1% Firm-Stable
    PEEK Resin (Domestic Std.) ¥300,000–400,000/ton +1% Slight Up
    Carbon Fiber (T300/T700) ¥80–150/kg +1% Bottom Reversal
    PI Film (Std./High-End) ¥240,000–3,000,000/ton 0%~+0.5% High-End Strong
    Specialty Ceramic Raw Mats. ¥2,700–300/kg +0.5% Mild Rise

    Key Movements

    • PTFE Resin: +1% (Consolidating at highs after a ~30% surge in July; fluorspar/HF-acid cost support persists, and the industry’s “output control & price protection” discipline stays firm)
    • Carbon Fiber: +1% (Bottom reversal confirmed. Toray’s Jan +10–20% hike and Jilin Chemical Fiber follow-through, plus low-altitude-economy eVTOL demand, with inventories falling from highs)
    • High-End PI Film: Firm (Kaneka raised all PI film prices 20% in April; AI-server/Rubin and HBM demand lock the high-end electronic-grade supply deficit through 2027)

    Impact Analysis

    • Procurement Cost: PTFE at a relative high pressures anti-corrosion/sealing costs — lock 2–3 months of inventory. Carbon fiber at historic lows benefits wind-blade and aero-composite buyers. High-end PI film is costly — place orders 3 months ahead.
    • Supply Chain: PTFE fluorspar tightness extends supplier lead times; carbon fiber’s ~86% localization boosts autonomy; high-end PI/PEEK remain import-dependent — watch FX and geopolitical logistics risk.

    Action Recommendations

    • Lock In Now: PTFE resin (cost-push, hard to fall — lock 2–3 months immediately), High-end PI film (supply deficit — pre-stock)
    • Hold & Watch: Carbon fiber (rebound but high inventory — buy in batches), PEEK industrial grade (domestic capacity caps price — JIT), Specialty ceramic raw materials (ample supply — JIT)