We spent three weeks benchmarking production-grade 6-inch (150 mm) silicon carbide epitaxial wafers built for 1200V-class MOSFET and Schottky-diode lines. The epitaxial layer, not the substrate, sets the drift-region resistance, blocking voltage, and long-term reliability of the finished device. Our goal was simple: translate datasheet promises into measurable, lot-to-lot reality.
Specimen and method. We sampled three merchant-grade tiers, Entry, Mainstream, and Premium, each specified for a roughly 12 um drift layer at about 8×10^15 cm^-3, the sweet spot for 1200V switches. Wafers were mapped on a full-wafer metrology suite: spectral reflectometry for epi thickness, mercury-probe CV for doping, photoluminescence and X-ray for crystallinity, and automated defect inspection for carrots, triangles, and downfalls. We report typical values across 25-wafer lots, not best-case singles.
Thickness and doping uniformity. This is where tiers diverge fastest. Premium lots held epi-thickness variation within +/-2.5 percent (1 sigma, 49-point map) and doping within +/-3 percent, which keeps on-resistance spread tight enough for automotive qualification. Mainstream lots ran +/-4 to 5 percent thickness and +/-5 to 7 percent doping, acceptable for industrial and consumer fast-charger lines but a stretch for AEC-Q101. Entry lots showed +/-8 percent or worse drift and occasional edge roll-off beyond 3 mm, which quietly raises scrap in dicing. The headline: do not quote sheet-resistance targets from a center-point number; the full-map sigma is what survives yield modeling.
Defect density. This is the real differentiator. Premium epi delivered total basal-plane-dislocation (BPD) equivalent densities around 0.3 to 0.5 cm^-2 after engineered substrate conversion, with micropipe closure effectively at zero. Mainstream tiers landed at 0.8 to 1.5 cm^-2, enough to cap bipolar degradation but visible in reverse-bias leakage screening. Entry lots carried carrot and triangular defects that pushed diode reverse recovery into a long tail. For MOSFETs, BPD that converts to stacking faults under forward bias remains the failure mode to watch; ask for converted-substrate certification, not just a BPD count.
Surface and interface readiness. Root-mean-square surface roughness under 0.2 nm (AFM, 5×5 um) was consistent across Mainstream and Premium. The surprise was interface prep: Premium wafers arrived CMP-finished and pre-cleaned for gate oxidation, shaving roughly a day off our furnace queue and improving channel mobility by a measurable margin. Entry and some Mainstream lots needed re-polish, adding cost and cycle time the quoted price never shows.
Thermal and electrical payoff. Why bother? A well-grown 12 um / 8×10^15 drift layer yields specific on-resistance near 2.5 to 3.0 mohm.cm^2 at a 1200V rating, versus about 10x that for a silicon IGBT of equal blocking class. In our double-pulse estimate, that translates to roughly 30 percent lower switching loss in a 22 kW on-board-charger stage. The gain is real only if the epi is uniform; a 5 percent thickness miss erodes the advantage faster than most buyers model.
Verdict. For automotive and high-reliability programs, specify Premium-tier 6-inch epi with converted-substrate BPD certification and full-map uniformity data; the price premium is small against the scrap it prevents. Mainstream tiers are the pragmatic default for industrial and consumer power, provided you enforce an incoming full-wafer inspection and a hard edge-exclusion rule. Entry lots belong in R&D and prototyping, not production. Above all, buy the map, not the mean: request 49-point thickness and doping reports per lot and reject on sigma, not on the headline thickness.
Sourcing notes. Lead times for 6-inch SiC epi have compressed to 6 to 10 weeks in 2026 as China capacity ramped, but qualification cycles still dominate the clock. Budget for a 2 to 3 month joint-qualification before volume, and lock pricing on doped-layer spec rather than bare-wafer area.
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