Sapphire Substrate Sourcing Guide (2026): Orientation and Miscut, Size Economics, Quality Specs and China Price Benchmarks for LED and RF Buyers

Sapphire (single-crystal Al2O3) remains the default substrate for gallium nitride (GaN) LED epitaxy and a credible platform for RF and power GaN devices. For procurement teams buying from China in 2026, the question is no longer “sapphire or not” — it is how to lock orientation, crystal-growth route, geometric quality parameters and incoming verification before the first purchase order. This guide covers the specs that belong in your RFQ, the size economics that dominate landed cost, and the verification steps that prevent a container of beautiful-looking but epitaxy-hostile wafers.

1. What you are actually buying

A sapphire substrate is a polished slice of a grown single crystal. The growth method determines internal quality and price simultaneously:

• HEM (Heat Exchanger Method) — large boules, low dislocation density near the seed, strong yield on 4–6 inch; the mainstream route for LED-grade material.
• KY (Kyropoulos) — very large crystals, excellent for 6–8 inch wafers; the dominant cost-competitive route in China.
• EFG (Edge-defined Film-fed Growth) — grows sheets directly, lowest cost per square centimeter, but carry-over of growth artifacts (inclusions, bubble lines) requires tighter incoming inspection.
• CZ (Czochralski) — mature but less common for large-area LED wafers today.

In your RFQ, always state the growth method (or ask the supplier to declare it) plus whether the material is true epi-ready (epi-polished) or only mechanically polished. A mechanically polished wafer that “looks the same” will poison an MOCVD run within hours.

2. Orientation and miscut: the parameter nobody negotiates after signing

Sapphire is anisotropic. The crystallographic plane you buy defines your entire downstream process:

• C-plane (0001) with 0.2° miscut toward the A-axis — the standard for GaN-on-sapphire LED and power epitaxy. The miscut step density controls GaN nucleation; an unspecified miscut is a recipe for film morphology defects.
• R-plane (1-102) — used for silicon-on-sapphire and some GaN device work.
• M-plane / A-plane — niche nonpolar or semi-polar epitaxy and optical applications.

Specify: plane index, miscut angle tolerance (±0.1° to ±0.2° is commercial practice), and miscut direction as a crystallographic reference, not “as usual”. Ask for an X-ray orientation certificate per lot — a cent-level check that protects an epitaxy campaign worth tens of thousands of dollars.

3. The 12-item RFQ specification sheet

• 1. Diameter: 2″ (50.8 mm), 4″ (100 mm), 6″ (150 mm), 8″ (200 mm) — declare edge profile.
• 2. Thickness: e.g., 430 µm (2″), 650 µm (4″), 1000–1300 µm (6″) — must match your carrier and backgrind plan.
• 3. Orientation: C(0001) ±0.2° miscut, direction declared.
• 4. Growth method declared (KY / HEM / EFG).
• 5. Surface finish: epi-ready; both sides epi-polished or one side polished + ground backside — declare explicitly.
• 6. Ra (front surface): ≤ 0.3 nm typical for epi-ready; require AFM certificate on a sampling plan.
• 7. TTV / BOW / WARP: common commercial limits are TTV ≤ 10 µm, BOW ≤ 10 µm, WARP ≤ 15 µm on 4″; relax with caution on 6–8 inch, since lithography and the MOCVD wafer carrier both care.
• 8. Dislocation density: declare method (e.g., etch-pit) and typical level; LED-grade material is commonly quoted in the 10^3–10^5 cm⁻² range depending on grade and position in boule.
• 9. Edge exclusion and usable area: state laser-scribed or diced edge handling.
• 10. Surface inspection class: particle counts, scratches, digs per a stated inspection standard under defined lighting.
• 11. Primary orientation flat length and secondary flat convention.
• 12. Packaging: cassettes, optional N2 purge, per-wafer barcodes traceable to boule and ingot position.

4. Size economics: why 6-inch changes the math

China’s sapphire industry has ramped 6-inch capacity aggressively. The unit-area price advantage of 6 inch over 4 inch is real but conditional: it only materializes if your epitaxy toolset, lithography alignment and downstream processing actually support the larger wafer. Typical considerations:

• 4 inch — lowest switching cost, broadest tool compatibility; the safe volume platform for most LED buyers in 2026.
• 6 inch — 2.25× area per wafer; usually the best total-cost option once the MOCVD fleet is 6-inch-qualified. Price per cm² commonly undercuts 4 inch; verify the quoting convention (per wafer vs per cm²).
• 8 inch — strategic capacity ramp; lot-to-lot consistency is still the main risk. Pilot quantities and dual sourcing recommended before committing volume.
• 2 inch — now mostly R&D, specialty RF and small-batch device work; worst price per area, logistics dominate.

5. 2026 China price benchmarks (indicative ranges)

Prices are given as reference ranges for budgeting only; confirm spot pricing with at least three suppliers at RFQ time:

• 2″ epi-ready C-plane: roughly USD 4–12 per wafer depending on grade and volume.
• 4″ epi-ready C-plane: roughly USD 10–30 per wafer.
• 6″ epi-ready C-plane: roughly USD 20–55 per wafer.
• 8″ pilot lots: negotiated per project, wide dispersion.

Two levers move quotes more than any others: annual volume commitment (price tiers of 10–25% between 10k and 500k wafers per year are normal) and specification relaxation on TTV/BOW/WARP for applications that can tolerate it (e.g., non-lithographic optical windows). Never relax orientation tolerance — it is nearly free for the supplier to hold and catastrophically expensive for you to lose.

6. Five-step sourcing workflow

• Step 1 — Lock the spec sheet (Section 3) into the RFQ; reject quotes that do not answer every line item.
• Step 2 — Samples + certificates: request 10–25 wafers from at least two boules, with X-ray orientation report, AFM Ra scan, and a per-wafer TTV/BOW/WARP map.
• Step 3 — Epitaxy qualification: run the sample wafers through your standard MOCVD buffer-layer process; compare nucleation uniformity, post-growth warpage and PL peak-wavelength mapping against incumbent material.
• Step 4 — Incoming verification in the contract: put the AQL sampling plan, acceptance tests (X-ray orientation spot check, TTV/WARP 100% or sampled, visual inspection standard) and rejection/recourse terms in the purchase agreement — not in email.
• Step 5 — Batch traceability: require boule ID and ingot position on every cassette; dislocation density varies within a boule and edge wafers behave differently.

7. Five expensive mistakes

• 1. Accepting “C-plane” without a declared miscut angle and direction.
• 2. Mixing EFG material into a KY-qualified process without requalification.
• 3. Comparing per-wafer quotes across different thicknesses and edge treatments.
• 4. Skipping the post-growth warpage check — a substrate within BOW spec can still produce out-of-spec warped epi wafers.
• 5. Buying “polished” instead of “epi-ready” to save 15% — the MOCVD run you lose costs 50× more.

8. FAQ

Q: Can sapphire be replaced by SiC or silicon for my LED line?
A: Not line-for-line. SiC offers better thermal conductivity at a much higher wafer price; silicon offers scale but struggles with GaN crack management and loses transparency for vertical structures. Most mid-volume LED production in 2026 remains GaN-on-sapphire for good reason.

Q: What MOQ should I expect from Chinese suppliers?
A: Sample lots of 25–100 wafers are routine; volume pricing typically starts at 1,000–5,000 wafers per size, with deeper tiers at 50k+.

Q: How can incoming inspection catch most problems cheaply?
A: Three checks catch most issues: geometric mapping (TTV/BOW/WARP), an X-ray orientation spot check, and epi-grade polish verification via dark-field visual plus periodic AFM. Dislocation density is best left to the supplier certificate plus periodic third-party verification.

Q: Is 8-inch sapphire ready for volume orders?
A: Capacity exists, but treat 2026 as pilot-scale: dual-source, run qualification lots each quarter, and negotiate requalification terms into the contract.

All prices in this guide are indicative budgeting ranges as of October 2026 and must be re-verified with suppliers at RFQ time. Tolerances and inspection conventions cited are common commercial practice; confirm the current published edition before contract signature.