As silicon carbide (SiC) power devices move from boutique deployments into mainstream electric vehicles, solar inverters, and fast-charging infrastructure, the epitaxial wafer has become the true bottleneck of the supply chain. For procurement teams building MOSFETs and Schottky diodes, the SiC epitaxial wafer (6-inch) is now the volume workhorse: it balances the cost advantages of larger diameters with a manufacturing base that is mature enough for automotive qualification. This guide explains what buyers must specify, how to qualify suppliers, and where the 2026 market is heading.
What Is a SiC Epitaxial Wafer?
A SiC epitaxial wafer starts with a conductive or semi-insulating SiC substrate, onto which a thin, high-purity monocrystalline layer—the “epitaxial” or “epi” layer—is grown, usually by chemical vapor deposition (CVD). It is this epi layer, not the substrate, that carries the active device. For a 1,200 V MOSFET or a fast-recovery diode, the epi layer provides the drift region where voltage is sustained, so its thickness, doping, and crystal quality directly determine breakdown voltage, on-resistance, and leakage.
When buyers ask for a SiC epitaxial wafer (6-inch), they are requesting an epi-ready 150 mm substrate with a CVD-grown layer meeting device-specific specs. The diameter matters: 6-inch wafers roughly double the die count versus 4-inch for the same die size, spreading fixed processing cost and lifting yield economics.
Specifications Procurement Teams Must Define
A purchase order that only says “6-inch SiC epi” will produce inconsistent lots. Specify these parameters explicitly:
- Epi thickness and tolerance. Power MOSFETs at 650–1,200 V typically need 6–12 µm of drift layer; 1,700 V+ devices need more. State the target and ± tolerance.
- Doping concentration. Drift-layer doping in the 10¹⁵ cm⁻³ range sets on-resistance; tight control avoids field-crowding failures.
- Surface roughness (Ra). Target ≤ 0.2 nm to protect gate-oxide reliability in MOSFETs.
- Defect density. Carrot defects, triangles, downfalls, and micropipes must be bounded; ask for a map and a classified defect count per wafer.
- Thickness/doping uniformity. CV-measured across-wafer uniformity should be tight (typically ≤ 3% for thickness) to keep device parametric spread low.
- Basal-plane dislocation (BPD) density. Low BPD reduces bipolar degradation in body diodes.
Buyers should attach an acceptance limit—AQL or ppm-based—so incoming inspection is objective.
Why 6-Inch, and Not 4-Inch or 8-Inch?
Four-inch lines still exist but are being retired for cost reasons; the die-per-wafer gap is simply too large at volume. Eight-inch (200 mm) SiC epi is in early pilot production in 2026 and promises further economy, but substrate bow, epitaxial stress, and tool availability keep it pre-production for most buyers. The SiC epitaxial wafer (6-inch) sits in the sweet spot: tools are qualified, fabs are ramped, and automotive programs have validated the source. For a 2026 procurement plan, 6-inch is the safe default unless you are locked to a legacy 4-inch line.
Evaluating and Qualifying Suppliers
The global supplier base spans Japan, Europe, the United States, and an expanding Chinese cluster. For overseas buyers, China has become a major source of cost-competitive 6-inch SiC epi, but qualification discipline is non-negotiable:
- Audit the substrate source. Epi quality tracks substrate quality. Confirm whether the vendor grows its own substrates or buys them, and review the substrate’s micropipe and BPD pedigree.
- Request a qualification lot. Run three consecutive lots through your line; track parametric yield, not just visual pass.
- Demand traceability. Per-wafer maps for thickness, doping, and defects should accompany every shipment.
- Check automotive credentials. IATF 16949 and PPAP capability matter if you serve EV or charging customers.
- Confirm capacity and lead time. SiC epi lead times can stretch; lock allocation for the quarterly volume you commit to.
Incoming Inspection and Quality Verification
Do not trust the CoA alone. A practical incoming plan:
- Sample for CV profiling (thickness + doping uniformity) at center and edge.
- Run a surface scan for particles and morphology defects.
- Cross-section one wafer per lot for epi/substrate interface integrity.
- Track lot-to-lot drift with a control chart; reject on trend, not just on point failure.
This catches the subtle uniformity drift that ruins MOSFET threshold-voltage spread before it reaches your fab.
Cost Structure and Pricing Levers
SiC epi pricing in 2026 is driven by substrate cost (still the dominant element), CVD tool throughput, yield, and wafer diameter. Levers buyers can pull:
- Volume commitment in exchange for fixed pricing and priority allocation.
- Spec tightening discipline—over-specifying uniformity you cannot use raises cost with no benefit.
- Dual-sourcing to keep spot leverage without qualifying risk.
- Lot-size alignment with your fab’s batch to cut handling and quarantine overhead.
Expect per-wafer quotes to vary widely by spec; compare like-for-like, never headline price alone.
Common Procurement Pitfalls
- Treating epi and substrate as one undifferentiated “wafer.”
- Skipping the three-lot qualification in favor of a single sample.
- Ignoring BPD and basal-plane dislocation data until field returns appear.
- Chasing the lowest price on 8-inch pre-production material before the supply chain is ready.
- Losing traceability when scaling from engineering to volume.
Outlook for 2026
Demand for the SiC epitaxial wafer (6-inch) is set to grow as 800 V EV platforms and 350 kW charging proliferate. Supply is tightening but diversifying, with Chinese capacity additions easing the substrate constraint. Buyers who lock qualified 6-inch sources now, with disciplined specs and inspection, will protect both cost and yield through the next demand wave.
If your team is scoping a 2026 SiC epi sourcing program, start with a three-lot qualification on a clearly specified 6-inch drift layer and build your supplier scorecard around parametric yield—not price alone.
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