Why 6-inch SiC Epitaxial Wafers Are the 2026 Bottleneck Everyone Is Talking About
If you are buying power semiconductors in 2026, you have already felt the pull of silicon carbide. EV traction inverters, 800 V fast-charging stations, solar string inverters and industrial motor drives are all migrating from silicon IGBTs to SiC MOSFETs — and every one of those devices is built inside a thin silicon carbide epitaxial layer grown on top of a substrate. The substrate is just the foundation; the epitaxial (“epi”) layer is where the device actually lives. For most discrete and module buyers, the part you are really qualifying is the epitaxial wafer, not the bare substrate.
China is now the single largest capacity base for 6-inch (150 mm) SiC, spanning crystal growth, substrate slicing/polishing, and homoepitaxy. That makes it the default sourcing region for cost-sensitive volume programs — provided you know exactly what to specify. This guide walks overseas procurement and engineering buyers through a specification-driven, low-risk path to sourcing 6-inch SiC epitaxial wafers from China.
What an SiC Epitaxial Wafer Actually Is
An SiC epitaxial wafer is a two-part stack:
- Substrate: a monocrystalline 4H-SiC wafer (usually off-axis cut) that provides the crystal lattice.
- Epitaxial layer: a thin, device-grade 4H-SiC film grown on the substrate surface by chemical vapor deposition (CVD). This drift layer is doped to form the voltage-blocking region of the MOSFET or diode.
For 2026 programs, 6-inch / 150 mm is the dominant wafer size — it halves die cost versus 4-inch and is where most new Chinese capacity is landing. The “6-inch” refers to the wafer diameter; the value is in the epi layer specs, not the diameter.
Your RFQ Spec Sheet: What to Put in Writing
Ambiguous specs are the #1 cause of rejected lots. Lock the following parameters in your purchase order and your supplier’s certificate of analysis (COA):
| Parameter |
What to specify |
Typical 2026 range |
| Wafer diameter |
150 mm (6-inch), single-crystal |
150.0 ± 0.2 mm |
| Polytype / orientation |
4H-SiC, 4°±0.5° off (0001) toward <11-20> |
n/a |
| Substrate micropipe density |
Zero-pipe target |
0 cm⁻² (max 0.1) |
| Substrate BPD / TSD / TED |
Low BPD is critical for bipolar yield |
BPD < 200 cm⁻², TSD < 500 cm⁻² |
| Epi thickness (drift) |
Match your blocking voltage |
650 V ≈ 5–6 µm; 1200 V ≈ 10–12 µm; 1700 V ≈ 15–18 µm |
| Epi doping (drift) |
N-type (nitrogen), with tolerance |
1×10¹⁵ – 1×10¹⁶ cm⁻³ |
| Epi thickness uniformity |
Across-wafer |
± 3–5% (1σ) |
| Surface roughness (epi) |
Post-CMP, AFM |
Ra < 0.2–0.5 nm |
| Epi defect density |
Triangular, carrot, downfall, comet |
Agreed max counts / wafer |
| Epitaxial stacking faults |
Basal-plane SF density |
Per-map limit |
| Packaging |
Single-wafer cassette, ESD-safe |
N₂-purged, moisture barrier |
Evaluate on Specifications, Not on Promises
Keep the evaluation focused on the product. A disciplined, spec-driven incoming process protects yield far better than paperwork:
- Request the COA with full maps. Insist on wafer-level epi thickness maps, doping (CV) profiles, and PL/XRD defect maps — not just single-point numbers.
- Run incoming inspection. Photoluminescence (PL) mapping for defects, CV for doping, ellipsometry or FTIR for thickness, AFM for roughness. A small third-party metrology check on the first lot pays for itself.
- Qualify on a sample lot. Run the lot through your own fab or a test house; correlate epi defect density with final device yield before committing to volume.
- Define acceptance limits contractually. Put max allowable triangular/carrot defect counts and SF density in the PO so disputes are objective.
Logistics, Packaging and Documents
- Packaging: single-wafer cassettes, ESD-shielded, nitrogen-purged, with desiccant and moisture-barrier bag. Shock and static are the two transit killers.
- HS classification: semiconductor-grade SiC wafers are commonly declared under HS 3818.00 (prepared semiconductor articles) or 8541.90 (parts of semiconductor devices). Confirm the exact code with your customs broker — classifications vary by import country.
- Lead time: qualified 6-inch epi typically runs 8–16 weeks; tighter defect specs extend it. Plan replenishment accordingly.
- Incoterms & docs: FOB Shanghai / Shekou is common; request commercial invoice, packing list, certificate of origin and the COA with every shipment.
Cost Structure and Landed Cost
The substrate is the dominant cost; the epitaxial growth step typically adds a 30–60% premium on top of the bare substrate, driven by defect-density requirements and layer thickness. Your landed cost is:
Ex-works price + international freight + insurance + import duty + VAT/brokerage
In 2026, 6-inch capacity is ramping fast, so standard-grade epi prices are softening, but tight-spec epi (ultra-low BPD, near-zero triangular defects) still commands a premium. Volume commitments and multi-year frameworks are the levers that move unit price.
Five Pitfalls That Burn Buyers
- Confusing substrate grade with epi spec. A great substrate can still have a poor epi layer. Qualify the epi.
- Accepting high BPD. Basal-plane dislocations seed stacking faults in bipolar devices and kill yield.
- Ignoring epi defect density. Triangular and carrot defects are die killers — set hard limits.
- Skipping incoming PL/XRD maps. You cannot manage what you do not measure.
- Underestimating lead time and ESD risk. Both cause line-down emergencies.
RFQ Checklist (Copy This)
| Item |
Confirm before PO |
| Wafer size & orientation |
150 mm, 4H-SiC, 4° off-axis |
| Epi thickness & voltage target |
e.g., 10–12 µm for 1200 V |
| Doping & tolerance |
N-type, 1e15–1e16 cm⁻³ |
| Defect limits (contractual) |
Triangular / carrot / SF max counts |
| COA with maps |
Thickness, CV, PL/XRD per wafer |
| Sample-lot qualification |
Yield correlation agreed |
| Packaging & lead time |
N₂ cassette, 8–16 weeks |
| HS code & docs |
Confirmed with broker |
Work With a Sourcing Partner
Specifying and qualifying 6-inch SiC epitaxial wafers is a metrology-heavy process. LiiFoo helps overseas buyers build a specification-driven China sourcing workflow — from RFQ spec sheets and sample-lot qualification to COA review, incoming-inspection coordination and full logistics. Request a quote and we will help you lock the right epi specs for your 2026 program.