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  • 连续纤维增强热塑性复合材料CFRTP: Complete Procurement & Application Guide

    连续纤维增强热塑性复合材料CFRTP: Complete Guide for Global Buyers

    What is 连续纤维增强热塑性复合材料CFRTP?

    连续纤维增强热塑性复合材料CFRTP represents one of the most dynamic segments in advanced materials R&D, with applications spanning new energy, semiconductors, aerospace, and next-generation manufacturing.

    Market Outlook

    Driven by accelerating adoption in key industries, 连续纤维增强热塑性复合材料CFRTP is experiencing rapid demand growth. Several Chinese manufacturers have made significant progress in scaling production and achieving international certifications.

    Procurement Considerations

    When sourcing 连续纤维增强热塑性复合材料CFRTP, buyers should evaluate: purity specifications, particle size distribution, packaging standards, compliance certifications (ISO, ASTM, REACH), and the supplier’s technical documentation and support capabilities.

    📩 Need Samples or Technical Specifications?

    Our engineering team provides material selection support, free samples, and custom quotes for 连续纤维增强热塑性复合材料CFRTP.
    👉 Request Quote & Samples

  • 玻璃基板芯片封装材料：Complete Procurement & Application Guide

    玻璃基板芯片封装材料：Complete Guide for Global Buyers

    什么是玻璃基板芯片封装材料？

    玻璃基板芯片封装材料是当前全球新材料领域的热门研究方向，广泛应用于新能源、半导体、航空航天等高端制造场景。

    市场规模与发展趋势

    随着下游应用场景的快速扩展，玻璃基板芯片封装材料的市场需求呈现快速增长态势。预计未来3-5年内，将有更多国内企业实现技术突破和量产。

    选型要点与采购建议

    在采购玻璃基板芯片封装材料相关材料时，需要重点关注：纯度等级、粒径分布、包装规格、认证标准，以及供应商的技术支持能力。

    📩 需要样品或详细规格？

    我们的工程师团队可以为您提供材料选型建议、免费样品及定制报价。
    👉 点击获取报价 & 样品

  • 碳化硅功率器件SiC MOSFET：Complete Procurement & Application Guide

    碳化硅功率器件SiC MOSFET：Complete Guide for Global Buyers

    什么是碳化硅功率器件SiC MOSFET？

    碳化硅功率器件SiC MOSFET是当前全球新材料领域的热门研究方向，广泛应用于新能源、半导体、航空航天等高端制造场景。

    市场规模与发展趋势

    随着下游应用场景的快速扩展，碳化硅功率器件SiC MOSFET的市场需求呈现快速增长态势。预计未来3-5年内，将有更多国内企业实现技术突破和量产。

    选型要点与采购建议

    在采购碳化硅功率器件SiC MOSFET相关材料时，需要重点关注：纯度等级、粒径分布、包装规格、认证标准，以及供应商的技术支持能力。

    📩 需要样品或详细规格？

    我们的工程师团队可以为您提供材料选型建议、免费样品及定制报价。
    👉 点击获取报价 & 样品

  • Comprando Pastilhas Epitaxiais de SiC de 6 Polegadas na China em 2026: Guia de Suprimento para Compradores de Dispositivos de Potência

    Por que as pastilhas epitaxiais de SiC de 6 polegadas são o gargalo de 2026

    Se você compra semicondutores de potência em 2026, já sentiu a atração do carboneto de silício. Inversores de tração para veículos elétricos, estações de carregamento rápido 800 V, inversores solares string e acionamentos de motores industriais estão migrando dos IGBTs de silício para os MOSFETs de SiC — e todos esses dispositivos são construídos dentro de uma fina camada epitaxial de carboneto de silício crescida sobre um substrato. O substrato é apenas a base; a pastilha epitaxial é onde o dispositivo de fato vive.

    A China é hoje a maior base de capacidade de SiC de 6 polegadas (150 mm) do mundo, abrangendo crescimento de cristal, corte e polimento de substratos e a homoepitaxia. Isso a torna a região de suprimento padrão para programas de volume sensíveis a custo — desde que você saiba exatamente o que especificar. Este guia conduz compradores e engenheiros estrangeiros por um caminho de suprimento da China, orientado por especificações e de baixo risco, para pastilhas epitaxiais de SiC de 6 polegadas.

    O que é, afinal, uma pastilha epitaxial de SiC

    Uma pastilha epitaxial de SiC é uma estrutura de duas camadas:

    • Substrato: uma wafer monocristalina de 4H-SiC (geralmente corte fora do eixo) que fornece a rede cristalina.
    • Camada epitaxial: uma fina película de 4H-SiC de grau dispositivo crescida na superfície do substrato por deposição química a vapor (CVD). Essa camada de deriva é dopada para formar a região de bloqueio de tensão do MOSFET ou diodo.

    Nos programas de 2026, 6 polegadas / 150 mm é o tamanho dominante — reduz pela metade o custo por die em relação a 4 polegadas e é onde a nova capacidade chinesa está se concentrando. “6 polegadas” refere-se ao diâmetro; o valor está nas especificações da camada epitaxial, não no diâmetro.

    Sua ficha de especificações (RFQ): o que colocar por escrito

    Especificações vagas são a principal causa de lotes rejeitados. Trave os seguintes parâmetros no pedido e no certificado de análise (COA) do fornecedor:

    Parâmetro O que especificar Faixa típica em 2026
    Diâmetro da wafer 150 mm (6 polegadas), monocristalina 150,0 ± 0,2 mm
    Polítipo / orientação 4H-SiC, 4°±0,5° fora do eixo (0001) para <11-20> n/d
    Densidade de microtubos Alvo de zero microtubo 0 cm⁻² (máx. 0,1)
    BPD / TSD / TED do substrato BPD baixo é crítico para rendimento bipolar BPD < 200 cm⁻², TSD < 500 cm⁻²
    Espessura epi (deriva) Conforme a tensão de bloqueio 650 V ≈ 5–6 µm; 1200 V ≈ 10–12 µm; 1700 V ≈ 15–18 µm
    Dopagem epi (deriva) Tipo N (nitrogênio), com tolerância 1×10¹⁵ – 1×10¹⁶ cm⁻³
    Uniformidade de espessura Em toda a wafer ± 3–5% (1σ)
    Rugosidade superficial (epi) Pós-CMP, AFM Ra < 0,2–0,5 nm
    Densidade de defeitos epi Triangular, cenoura, queda, cometa Máx. acordado por wafer
    Falhas de empilhamento Densidade de SF de plano basal Limite por mapa
    Embalagem Porta-wafer individual, anti-ESD Purga N₂, barreira à umidade

    Avalie pelas especificações, não por promessas

    Mantenha a avaliação focada no produto. Um processo de inspeção de recebimento disciplinado e orientado por especificações protege o rendimento muito melhor do que papelada:

    • Peça o COA com mapas completos. Exija mapas de espessura epi por wafer, perfis de dopagem (CV) e mapas de defeitos PL/XRD — não apenas números de ponto único.
    • Faça inspeção de recebimento. Mapeamento por fotoluminescência (PL) para defeitos, CV para dopagem, elipsometria ou FTIR para espessura, AFM para rugosidade. Uma pequena verificação metrológica terceirizada no primeiro lote se paga.
    • Qualifique com lote-amostra. Submeta o lote à sua fab ou a um laboratório; correlacione a densidade de defeitos epi com o rendimento final antes de comprometer volume.
    • Defina limites de aceitação no contrato. Coloque contagens máximas de defeitos triangulares/cenoura e densidade de SF no pedido, tornando as disputas objetivas.

    Logística, embalagem e documentos

    • Embalagem: porta-wafer individual, blindagem anti-ESD, purga de nitrogênio, com dessecante e barreira à umidade. Choque e estática são os dois assassinos do transporte.
    • Classificação HS: wafers de SiC de grau semicondutor costumam ser declarados no HS 3818.00 (artigos preparados para semicondutores) ou 8541.90 (partes de dispositivos semicondutores). Confirme o código exato com seu despachante — varia conforme o país de importação.
    • Prazo de entrega: epi de 6 polegadas qualificado gira tipicamente em 8–16 semanas; especificações mais rigorosas estendem o prazo. Planeje o reabastecimento.
    • Incoterms e documentos: FOB Xangai / Shekou é comum; solicite fatura comercial, lista de embalagem, certificado de origem e o COA em cada envio.

    Estrutura de custo e custo total (landed cost)

    O substrato é o custo dominante; a etapa de crescimento epitaxial tipicamente adiciona prêmio de 30%–60% sobre o substrato nu, impulsionado pelos requisitos de densidade de defeitos e espessura. Seu custo total é:

    Preço à saída de fábrica + frete internacional + seguro + imposto de importação + IVA/despacho

    Em 2026, a capacidade de 6 polegadas está crescendo rápido, então os preços de epi de grau padrão estão recuando, mas epi de especificação rigorosa (BPD ultrabaixo, quase zero defeitos triangulares) ainda cobra prêmio. Compromissos de volume e frameworks multi-anuais são as alavancas de preço.

    Cinco armadilhas que prejudicam compradores

    • Confundir grau de substrato com especificação epi. Um bom substrato pode ter uma péssima camada epi. Qualifique a epi.
    • Aceitar alto BPD. Deslocações de plano basal geram falhas de empilhamento em dispositivos bipolares e destroem o rendimento.
    • Ignorar densidade de defeitos epi. Defeitos triangulares e cenoura matam dies — estabeleça limites rígidos.
    • Pular mapas PL/XRD de recebimento. Não se gerencia o que não se mede.
    • Subestimar prazo e risco ESD. Ambos causam paradas de linha.

    Checklist de RFQ (copie isto)

    Item Confirmar antes do pedido
    Tamanho e orientação 150 mm, 4H-SiC, 4° fora do eixo
    Espessura epi e tensão-alvo ex.: 10–12 µm para 1200 V
    Dopagem e tolerância Tipo N, 1e15–1e16 cm⁻³
    Limites de defeitos (contratuais) Máx. triangular / cenoura / SF
    COA com mapas Espessura, CV, PL/XRD por wafer
    Qualificação por lote-amostra Correlação de rendimento acordada
    Embalagem e prazo Cassete N₂, 8–16 semanas
    Código HS e documentos Confirmado com despachante

    Trabalhe com uma parceira de suprimento

    Especificar e qualificar pastilhas epitaxiais de SiC de 6 polegadas é um processo intensivo em metrologia. A LiiFoo ajuda compradores estrangeiros a construir um fluxo de suprimento da China orientado por especificações — do RFQ e qualificação de lote-amostra à revisão de COA, coordenação de inspeção de recebimento e logística completa. Solicite uma cotação e ajudaremos você a travar as especificações epi certas para o seu programa de 2026.

  • Sourcing 6-inch Silicon Carbide (SiC) Epitaxial Wafers from China in 2026: A Procurement Guide for Power-Device Buyers

    Why 6-inch SiC Epitaxial Wafers Are the 2026 Bottleneck Everyone Is Talking About

    If you are buying power semiconductors in 2026, you have already felt the pull of silicon carbide. EV traction inverters, 800 V fast-charging stations, solar string inverters and industrial motor drives are all migrating from silicon IGBTs to SiC MOSFETs — and every one of those devices is built inside a thin silicon carbide epitaxial layer grown on top of a substrate. The substrate is just the foundation; the epitaxial (“epi”) layer is where the device actually lives. For most discrete and module buyers, the part you are really qualifying is the epitaxial wafer, not the bare substrate.

    China is now the single largest capacity base for 6-inch (150 mm) SiC, spanning crystal growth, substrate slicing/polishing, and homoepitaxy. That makes it the default sourcing region for cost-sensitive volume programs — provided you know exactly what to specify. This guide walks overseas procurement and engineering buyers through a specification-driven, low-risk path to sourcing 6-inch SiC epitaxial wafers from China.

    What an SiC Epitaxial Wafer Actually Is

    An SiC epitaxial wafer is a two-part stack:

    • Substrate: a monocrystalline 4H-SiC wafer (usually off-axis cut) that provides the crystal lattice.
    • Epitaxial layer: a thin, device-grade 4H-SiC film grown on the substrate surface by chemical vapor deposition (CVD). This drift layer is doped to form the voltage-blocking region of the MOSFET or diode.

    For 2026 programs, 6-inch / 150 mm is the dominant wafer size — it halves die cost versus 4-inch and is where most new Chinese capacity is landing. The “6-inch” refers to the wafer diameter; the value is in the epi layer specs, not the diameter.

    Your RFQ Spec Sheet: What to Put in Writing

    Ambiguous specs are the #1 cause of rejected lots. Lock the following parameters in your purchase order and your supplier’s certificate of analysis (COA):

    Parameter What to specify Typical 2026 range
    Wafer diameter 150 mm (6-inch), single-crystal 150.0 ± 0.2 mm
    Polytype / orientation 4H-SiC, 4°±0.5° off (0001) toward <11-20> n/a
    Substrate micropipe density Zero-pipe target 0 cm⁻² (max 0.1)
    Substrate BPD / TSD / TED Low BPD is critical for bipolar yield BPD < 200 cm⁻², TSD < 500 cm⁻²
    Epi thickness (drift) Match your blocking voltage 650 V ≈ 5–6 µm; 1200 V ≈ 10–12 µm; 1700 V ≈ 15–18 µm
    Epi doping (drift) N-type (nitrogen), with tolerance 1×10¹⁵ – 1×10¹⁶ cm⁻³
    Epi thickness uniformity Across-wafer ± 3–5% (1σ)
    Surface roughness (epi) Post-CMP, AFM Ra < 0.2–0.5 nm
    Epi defect density Triangular, carrot, downfall, comet Agreed max counts / wafer
    Epitaxial stacking faults Basal-plane SF density Per-map limit
    Packaging Single-wafer cassette, ESD-safe N₂-purged, moisture barrier

    Evaluate on Specifications, Not on Promises

    Keep the evaluation focused on the product. A disciplined, spec-driven incoming process protects yield far better than paperwork:

    • Request the COA with full maps. Insist on wafer-level epi thickness maps, doping (CV) profiles, and PL/XRD defect maps — not just single-point numbers.
    • Run incoming inspection. Photoluminescence (PL) mapping for defects, CV for doping, ellipsometry or FTIR for thickness, AFM for roughness. A small third-party metrology check on the first lot pays for itself.
    • Qualify on a sample lot. Run the lot through your own fab or a test house; correlate epi defect density with final device yield before committing to volume.
    • Define acceptance limits contractually. Put max allowable triangular/carrot defect counts and SF density in the PO so disputes are objective.

    Logistics, Packaging and Documents

    • Packaging: single-wafer cassettes, ESD-shielded, nitrogen-purged, with desiccant and moisture-barrier bag. Shock and static are the two transit killers.
    • HS classification: semiconductor-grade SiC wafers are commonly declared under HS 3818.00 (prepared semiconductor articles) or 8541.90 (parts of semiconductor devices). Confirm the exact code with your customs broker — classifications vary by import country.
    • Lead time: qualified 6-inch epi typically runs 8–16 weeks; tighter defect specs extend it. Plan replenishment accordingly.
    • Incoterms & docs: FOB Shanghai / Shekou is common; request commercial invoice, packing list, certificate of origin and the COA with every shipment.

    Cost Structure and Landed Cost

    The substrate is the dominant cost; the epitaxial growth step typically adds a 30–60% premium on top of the bare substrate, driven by defect-density requirements and layer thickness. Your landed cost is:

    Ex-works price + international freight + insurance + import duty + VAT/brokerage

    In 2026, 6-inch capacity is ramping fast, so standard-grade epi prices are softening, but tight-spec epi (ultra-low BPD, near-zero triangular defects) still commands a premium. Volume commitments and multi-year frameworks are the levers that move unit price.

    Five Pitfalls That Burn Buyers

    • Confusing substrate grade with epi spec. A great substrate can still have a poor epi layer. Qualify the epi.
    • Accepting high BPD. Basal-plane dislocations seed stacking faults in bipolar devices and kill yield.
    • Ignoring epi defect density. Triangular and carrot defects are die killers — set hard limits.
    • Skipping incoming PL/XRD maps. You cannot manage what you do not measure.
    • Underestimating lead time and ESD risk. Both cause line-down emergencies.

    RFQ Checklist (Copy This)

    Item Confirm before PO
    Wafer size & orientation 150 mm, 4H-SiC, 4° off-axis
    Epi thickness & voltage target e.g., 10–12 µm for 1200 V
    Doping & tolerance N-type, 1e15–1e16 cm⁻³
    Defect limits (contractual) Triangular / carrot / SF max counts
    COA with maps Thickness, CV, PL/XRD per wafer
    Sample-lot qualification Yield correlation agreed
    Packaging & lead time N₂ cassette, 8–16 weeks
    HS code & docs Confirmed with broker

    Work With a Sourcing Partner

    Specifying and qualifying 6-inch SiC epitaxial wafers is a metrology-heavy process. LiiFoo helps overseas buyers build a specification-driven China sourcing workflow — from RFQ spec sheets and sample-lot qualification to COA review, incoming-inspection coordination and full logistics. Request a quote and we will help you lock the right epi specs for your 2026 program.

  • 6英寸碳化硅（SiC）外延片中国采购实战：规格锁定、RFQ清单与到岸成本（2026）

    为什么6英寸碳化硅（SiC）外延片是2026年最稀缺的环节

    如果你在2026年采购功率半导体，一定已经感受到碳化硅的拉力。电动汽车主驱逆变器、800V超充桩、光伏组串逆变器和工业电机驱动正从硅基IGBT大规模转向SiC MOSFET——而这些器件全部构建在一层生长在衬底之上的碳化硅外延层里。衬底只是地基，真正决定器件性能的是外延片，而不是裸衬底。

    中国已经是全球最大的6英寸（150mm）SiC产能基地，覆盖晶体生长、衬底切割抛光以及同质外延全链条。对于追求成本优势的规模化项目，中国是默认的采购区域——前提是你清楚该怎样指定规格。本指南为海外采购与研发买家梳理一条以规格驱动、低风险的6英寸SiC外延片中国采购路径。

    SiC外延片到底是什么

    SiC外延片是一个双层结构：

    • 衬底：单晶4H-SiC晶圆（通常为偏轴切割），提供晶体晶格。
    • 外延层：通过化学气相沉积（CVD）在衬底表面生长的器件级4H-SiC薄膜。这一漂移层经掺杂形成MOSFET或二极管的耐压区。

    在2026年的项目中，6英寸/150mm是绝对主流尺寸——相较4英寸可大幅降低单颗芯片成本，也是中国新增产能的主要落点。”6英寸”指的是晶圆直径，真正价值在于外延层的规格，而非直径本身。

    你的RFQ规格表：必须写进采购订单的内容

    规格模糊是来料被拒的首要原因。请在下单前与供应商的质检报告（COA）中锁定以下参数：

    参数 指定要求 2026年常见范围
    晶圆直径 150mm（6英寸），单晶 150.0 ± 0.2 mm
    晶型/取向 4H-SiC，偏轴4°±0.5°（0001）朝<11-20> —
    衬底微管密度 零微管目标 0 cm⁻²（最高0.1）
    衬底BPD/TSD/TED 低BPD对双极器件良率至关重要 BPD < 200 cm⁻²，TSD < 500 cm⁻²
    外延厚度（漂移层） 匹配耐压等级 650V≈5–6µm；1200V≈10–12µm；1700V≈15–18µm
    外延掺杂（漂移层） N型（氮），带公差 1×10¹⁵ – 1×10¹⁶ cm⁻³
    外延厚度均匀性 全片均匀性 ± 3–5%（1σ）
    表面粗糙度（外延） CMP后，AFM测试 Ra < 0.2–0.5 nm
    外延缺陷密度 三角形、胡萝卜、掉落、彗星缺陷 约定每片最大数量
    外延层错 基面层错（SF）密度 按图谱设定上限
    包装 单片刻盒，防静电 充氮、防潮屏障

    用规格评估，而不是用承诺评估

    评估请聚焦产品本身。以规格驱动、严谨的来料管控，比任何纸面资质都更能保障良率：

    • 索要带图谱的COA。坚持要求晶圆级外延厚度图、掺杂（CV）剖面以及PL/XRD缺陷图谱，而非单点数值。
    • 执行来料检验。用光致发光（PL）图谱查缺陷、CV测掺杂、椭偏或FTIR测厚度、AFM测粗糙度。首批次做一次小型第三方计量验证，回报远超成本。
    • 以样品批次做准入。将批次送入自有产线或测试机构，关联外延缺陷密度与最终器件良率，再决定是否放量。
    • 将验收上限写入合同。在PO中明确三角形/胡萝卜缺陷及SF密度的最大允许值，使争议可量化。

    物流、包装与单证

    • 包装：单片刻盒、防静电屏蔽、充氮、配干燥剂并置于防潮袋中。震动与静电是运输中的两大杀手。
    • HS编码：半导体级SiC晶圆通常归入HS 3818.00（半导体用制备品）或8541.90（半导体器件零件）。请与报关行确认进口国的准确税号。
    • 交期：合格6英寸外延片通常8–16周；规格越严交期越长，请据此规划补货。
    • 贸易术语与单证：常见FOB上海/蛇口；每批发货请索取商业发票、装箱单、原产地证及COA。

    成本结构与到岸成本

    衬底占成本主体；外延生长环节通常在裸衬底之上再加成30%–60%，由缺陷密度要求与厚度决定。你的到岸成本为：

    出厂价 + 国际运费 + 保险 + 进口关税 + 增值税/报关费

    2026年6英寸产能快速放量，标准规格外延价格持续下探，但严规格外延（超低BPD、近零三角形缺陷）仍享有溢价。长期框架与批量承诺是压低单价的关键杠杆。

    让买家吃亏的五个坑

    • 把衬底等级等同于外延规格。好衬底也可能长出差的外延层，请单独验收外延。
    • 接受高BPD。基面位错会在双极器件中诱发层错，直接摧毁良率。
    • 忽视外延缺陷密度。三角形与胡萝卜缺陷是芯片杀手，必须设硬上限。
    • 跳过来料PL/XRD图谱。无法度量就无法管理。
    • 低估交期与静电风险。两者都会导致产线停线。

    RFQ清单（可直接复制）

    项目 下单前确认
    晶圆尺寸与取向 150mm，4H-SiC，偏轴4°
    外延厚度与耐压目标 如1200V对应10–12µm
    掺杂与公差 N型，1e15–1e16 cm⁻³
    缺陷上限（合同化） 三角形/胡萝卜/SF最大数量
    带图谱的COA 逐片厚度、CV、PL/XRD
    样品批次准入 已约定良率关联
    包装与交期 充氮盒，8–16周
    HS编码与单证 已与报关行确认

    与专业采购伙伴同行

    指定并准入6英寸SiC外延片是一项高度依赖计量的工作。来芙社 LiiFoo 帮助海外买家建立以规格驱动的中国采购流程——从RFQ规格表、样品批次准入，到COA评审、来料检验协同与全程物流。欢迎获取报价，我们将帮助你为2026年项目锁定最合适的外延规格。

  • Glass Substrate for Advanced Chip Packaging: A 2026 Sourcing and Selection Guide

    Why Glass Substrate Is the Next Inflection Point in Advanced Packaging

    As AI accelerators, HPC and HBM high-bandwidth memory push packaging density and signal-integrity requirements ever higher, traditional organic substrates (BT and ABF) are hitting limits in warp control, coefficient of thermal expansion (CTE) matching and large-panel fan-out. Glass substrate — with its ultra-low tunable CTE, exceptional flatness, dimensional stability and processable through-glass-via (TGV) structures — is being advanced by Intel, Samsung and others as the mainstream next-generation carrier for advanced packaging.

    Core Material Advantages of Glass Substrates

    • Ultra-low, tunable CTE: Glass can be engineered close to silicon (~3–9 ppm/°C), sharply reducing thermal-mismatch warp between die and carrier and lifting large-format yield.
    • Superior flatness and surface roughness: Glass Ra can be an order of magnitude lower than organics, enabling finer line/space (L/S) routing and higher interconnect density.
    • Excellent dimensional stability: Glass is non-hygroscopic and isotropic, with minimal distortion at panel level (510×515 mm and above).
    • High-frequency electrical performance: Low dielectric loss supports high-speed signaling and RF integration.
    • TGV interconnect: Laser or chemical etching delivers high-aspect-ratio glass vias for 2.5D/3D vertical interconnect.

    Key Application Scenarios

    • 2.5D / 3D advanced packaging: As interposer or package substrate carrying high-density interconnect between GPU, CPU and HBM.
    • Panel-level packaging (FOPLP / FOPLP-G): Large glass panels pack more dies per batch, diluting per-unit cost.
    • RF and optical modules: Low loss and flatness suit antenna-in-package (AiP) and optical-engine integration.
    • Automotive and industrial high-reliability: Glass thermal and dimensional stability meet harsh-duty requirements.

    2026 Sourcing & Selection Checklist

    • Format and panel specs: Confirm wafer-level (300 mm) vs panel-level (510×515 mm, etc.) — this sets line and yield baselines.
    • Thickness and warp: Typical 0.1–1.0 mm; select per stack-up and thermal needs, with incoming TTV/warp within spec.
    • Surface roughness Ra / TGV aspect ratio: These directly determine achievable L/S and interconnect reliability.
    • CTE matching: Align with the CTE of the dice in use to avoid thermal-cycle failure.
    • Supplier qualification: Prioritize vendors with panel-glass volume experience, TGV process maturity and joint OSAT validation records.
    • Certification and lead time: Confirm automotive/industrial certification, MOQ and ramp cadence.

    Supply Landscape and Sourcing Advice

    Glass substrate is still early-commercial, with participants spanning display-glass leaders, semiconductor material suppliers and OSAT-led consortia. Buyers should engage via “low-volume validation plus joint process development,” landing first in lower cost-sensitivity, high-value scenarios such as RF and optical communications before scaling into large AI-compute packages. Watch TGV yield, panel-level equipment availability and material-to-packaging co-standardization.

    Conclusion

    Glass substrate is not a like-for-like replacement of organic carriers but a structural upgrade for ultra-large, ultra-dense packaging. For sourcing teams, 2026 is the window to lock in process know-how and qualified suppliers ahead of mainstream adoption.

  • 玻璃基板芯片封装材料：先进封装替代有机载板的2026采购与选型指南

    为什么玻璃基板成为先进封装的下一个风口

    随着 AI 加速卡、HPC 与 HBM 高带宽内存对封装密度与信号完整性要求的持续抬升，传统有机载板（BT 载板、ABF 载板）在翘曲控制、热膨胀系数（CTE）匹配与超大尺寸面板级封装上的瓶颈日益凸显。玻璃基板（Glass Substrate）凭借极低的 CTE、超高平整度、优异的尺寸稳定性与可加工的通孔玻璃（TGV, Through-Glass-Via）结构，正被 Intel、三星等头部厂商推进为下一代先进封装载板的主流方案。

    玻璃基板的核心材料优势

    • 超低且可调的 CTE：玻璃的 CTE 可做到与硅接近（约 3–9 ppm/°C），大幅缓解芯片与载板之间的热失配翘曲，提升大尺寸封装良率。
    • 超高平整度与表面粗糙度：玻璃表面粗糙度 Ra 可低于有机材料一个数量级，有利于细线宽/线距（L/S）布线，支持更高互连密度。
    • 优异的尺寸稳定性：玻璃无吸湿、各向同性，面板级（Panel-level）封装下畸变小，适合 510×515 mm 及以上大面板。
    • 高频电气性能：玻璃介电损耗低，有利于高速信号与射频集成。
    • TGV 通孔：通过激光或化学蚀刻实现高深宽比玻璃通孔，实现 2.5D/3D 垂直互连。

    主要应用场景

    • 2.5D / 3D 先进封装：作为中介层（interposer）或封装载板，承载 GPU、CPU 与 HBM 的高密度互连。
    • 面板级封装（FOPLP / FOPLP-G）：玻璃大面板支持更多颗芯片同批次封装，摊薄单位成本。
    • 射频与光通信模块：玻璃的低损耗与高平整度适合 AiP（天线封装）与光引擎集成。
    • 车规与工业高可靠场景：玻璃的耐温与尺寸稳定满足严苛工况。

    2026 采购选型 checklist

    • 尺寸与面板规格：确认是晶圆级（300 mm）还是面板级（510×515 mm 等），决定产线与良率基线。
    • 厚度与翘曲：常见 0.1–1.0 mm，按封装堆叠与散热需求选定，要求来料翘曲 TTV 达标。
    • 表面粗糙度 Ra / TGV 深宽比：直接决定可实现的线宽线距与互连可靠性。
    • CTE 匹配：与使用芯片的 CTE 对齐，避免热循环失效。
    • 供应商资质：优先具备面板玻璃量产经验、TGV 工艺与封装厂联合验证记录的厂商。
    • 认证与交期：确认车规/工规认证、最小起订量与量产爬坡节奏。

    供应链格局与采购建议

    目前玻璃基板处于商业化早期，参与者包括面板玻璃巨头、半导体材料厂商与封装厂联合阵营。采购方建议以“小批量验证 + 联合工艺开发”切入，先在射频/光通信等对成本敏感度较低的高价值场景落地，再向大算力封装规模导入。重点关注 TGV 良率、面板级封装设备配套与材料-封装协同标准的可获得性。

    结论

    玻璃基板不是对有机载板的简单替代，而是面向超大尺寸、超高密度封装的结构性升级。对采购而言，2026 年是提前锁定工艺窗口与合格供应商的关键窗口期。

  • 2026-08-25 New Materials Price Trend Daily Report

    2026-08-25 New Materials Price Trend Daily Report

    Price Overview

    Material Current Price Range WoW Trend
    PTFE Resin (Suspension Medium) 32,000-34,000 CNY/t -1.5% 📉 Down
    PEEK Resin (Industrial Grade) 320-500 CNY/kg +3.0% 📈 Up
    Carbon Fiber (T300/12K) 85-95 CNY/kg +1.5% 📈 Steady Rise
    PI Film (Electronic Grade) 280,000-1,500,000 CNY/t +4.0% 📈 Up (High-end Shortage)
    Specialty Ceramic Raw Material (Fused Zirconia) 33,000-34,000 CNY/t +1.5% 📈 Up

    Key Movements

    • PTFE Resin: -1.5%. Low-end general-purpose grades remain soft. Domestic PTFE capacity expanded rapidly through 2026, leaving supply ample; downstream chemical and oil & gas buyers purchase on demand with no concentrated restocking. Fluorite has pulled back to 3,250-3,350 CNY/t and crude oil to 68-72 USD/bbl, weakening cost support. Intensified competition has pushed trader quotes lower. Expected to oscillate within 31,000-35,000 CNY/t.
    • PEEK Resin: +3.0%. Global supply tightness drives the uptrend. Victrex capacity utilization has risen to ~95% with no new capacity before 2027; demand from semiconductor packaging, EV batteries, humanoid robots and eVTOL is expanding simultaneously, with Q2 2026 standard granules already ~8% higher YoY. Domestic industrial-grade offers strong value (30%-50% below imports), but the overall price center is moving up with DFBP monomer costs and FX.
    • PI Film (Electronic Grade): +4.0%. High-end shortage is worsening. Kaneka raised all PI film prices 20% in April and overseas majors (DuPont etc.) are up 30%-50% YTD; the global electronic-grade PI film gap has reached 10,000-12,000 t, with US/Japan/Korea leaders locked through 2027. Demand for high-thermal PI (AI servers) and PSPI (advanced packaging) is growing exponentially. Basic electrical grades are stable while high-end and CPI optical film (20-30M CNY/t) keep strengthening.
    • Specialty Ceramic Raw Material (Zirconia): +1.5%. Structural price gains are clear. Sinocera raised zirconia powder prices 10%-40% from July 27; yttria export controls triggered Tosoh’s shutdown, creating a ~6,000 t/yr rigid gap in global high-end nano-zirconia; fused zirconia is up ~27% YTD and standard zirconia ~29%. Downstream PCB grinding media, MLCC and solid-state batteries provide firm support.

    Impact Analysis

    • On Procurement Cost: PEEK, high-end PI film and yttria-stabilized zirconia are in an upward channel with supply constrained by locked orders and shutdowns, pressuring both spot cost and lead time. PTFE, by contrast, is a buyer’s market with low cost and ample negotiation room.
    • On Supply Chain: A “low-end loose, high-end tight” bifurcation persists. Carbon fiber, high-end PI film and YSZ have weak supply elasticity—secure long-term agreements and qualified suppliers early. Standard zirconia and PTFE are well supplied with low supply-chain risk.

    Action Recommendations

    • Lock prices now: PEEK resin (annual framework pricing), high-end electronic-grade PI film (qualify domestic substitutes early, lock long-term contracts), yttria-stabilized/nano-composite zirconia (domestic-substitution window—prioritize price and volume locks), T700+ carbon fiber (high-end shortage, build coverage early).
    • Monitor / wait: PTFE resin (low and soft—buy on demand, avoid stockpiling), standard electrical-grade PI film and standard zirconia (ample supply, prices track base feedstock—purchase opportunistically).

    Data sources: 100ppi, Mysteel, Baiinfo, public research and industry news. For reference only.

  • 2026-08-25 新材料价格趋势日报

    2026-08-25 新材料价格趋势日报

    价格概览表

    材料 当前价格区间 周环比 趋势
    PTFE树脂（悬浮中粒） 32,000-34,000 元/吨 -1.5% 📉 下行
    PEEK树脂（工业级） 320-500 元/公斤 +3.0% 📈 上涨
    碳纤维（T300/12K） 85-95 元/千克 +1.5% 📈 稳中有升
    PI薄膜（电子级） 280,000-1,500,000 元/吨 +4.0% 📈 上涨（高端紧缺）
    特种陶瓷原料（电熔氧化锆） 33,000-34,000 元/吨 +1.5% 📈 上涨

    重点变动

    • PTFE树脂：-1.5%。低端通用级延续偏弱。2026年以来国内PTFE产能快速扩张，供应宽松；下游化工、油气行业按需采购，缺乏集中补库；萤石回落至3,250-3,350元/吨、原油回落至68-72美元/桶，成本支撑减弱；厂商”内卷”致贸易商报价持续下探。预计31,000-35,000元/吨区间震荡。
    • PEEK树脂：+3.0%。全球供给偏紧推动上行。Victrex产能利用率升至约95%、2027年前无新增产能；半导体封装、EV电池、人形机器人、eVTOL需求同步放量，Q2 2026标准粒料同比已涨约8%。国产工业级性价比突出（较进口低30%-50%），但价格中枢随原料DFBP与汇率上移。
    • PI薄膜（电子级）：+4.0%。高端紧缺加剧。钟渊化学4月全系提价20%、杜邦等海外巨头年内涨30%-50%；全球电子级PI膜缺口达1-1.2万吨，美日韩龙头锁单至2027年；AI服务器高导热PI、先进封装PSPI需求指数级增长。基础电工级持稳，高端与CPI光学级（2000-3000万元/吨）持续走强。
    • 特种陶瓷原料（氧化锆）：+1.5%。结构性涨价明确。国瓷7月27日起上调氧化锆粉体10%-40%；氧化钇出口管制致日本东曹断供，全球高端纳米氧化锆出现约6000吨/年刚性缺口；电熔氧化锆年内涨约27%，普通氧化锆涨约29%。下游PCB研磨介质、MLCC、固态电池支撑刚性强。

    影响分析

    • 对采购成本：PEEK、高端PI膜、钇稳定氧化锆处于上行通道，且高端品供给受锁单与断供约束，现货采购成本与交期双重承压；PTFE则处于买方市场，采购成本低、议价空间大。
    • 对供应链：呈现”低端宽松、高端紧缺”的二元分化。碳纤维、高端PI膜、YSZ供给弹性弱，建议提前锁定长协与合格供应商；常规氧化锆、PTFE供应充足，供应链风险低。

    行动建议

    • 建议锁定价格：PEEK树脂（签年度框架价）、高端电子级PI膜（提前验证国产替代牌号、锁长协）、钇稳定氧化锆/纳米复合氧化锆（国产替代窗口期，优先锁价锁量）、T700及以上碳纤维（高端紧缺，提前布局）。
    • 建议观望：PTFE树脂（低位偏弱，按需采购即可，不宜囤货）、普通电工级PI膜与常规氧化锆（供应充足、价格随基础原料浮动，可择机采购）。

    数据来源：生意社、Mysteel、百川盈孚、公开研报及行业资讯。本报告仅供参考。