Verdict first: for power-electronics buyers, the SiC substrate market in 2026 is no longer a question of whether 4H-SiC wafers from China meet spec — volume suppliers now routinely do — but of which defect metrics you lock into the purchase contract and how much you are willing to pay for 200mm transition risk. After benchmarking wafer specs against device-fab requirements and current price bands, we rate n-type 4H-SiC substrates from qualified Chinese suppliers 4.5/5 for 150mm device-grade supply, and 3/5 for 200mm, where consistency is still maturing.
What the product actually is
A power-electronics-grade SiC substrate is a single-crystal 4H-SiC wafer, typically 350–500 μm thick, cut 4° off-axis toward the [11-20] direction to enable step-flow epitaxial growth, then chemo-mechanically polished to an epi-ready finish. Two commercial flavors dominate: n-type (nitrogen-doped, 0.015–0.030 Ω·cm) for MOSFETs and Schottky diodes, and semi-insulating (resistivity >10⁵ Ω·cm) for RF GaN-on-SiC. For EV traction inverters, solar string inverters and DC fast-charger modules — the demand engines of 2026 — it is the n-type 150mm wafer that moves in volume.
The defect benchmarks that actually matter
Marketing datasheets emphasize diameter and thickness; device fabs lose yield elsewhere. A serious spec sheet should commit to contractual values, not “typical” values, on five items:
- Micropipe density (MPD): ≤0.5 cm⁻² is now table stakes for device grade; leading Chinese material offers ≤0.1 cm⁻². Anything quoted as “<1 cm⁻² typical” belongs in R&D lots, not production.
- Basal plane dislocation (BPD) density: the silent killer of bipolar-degradation reliability in MOSFETs. Acceptable incoming range: ≤300 cm⁻² epi-ready, with BPD-to-threading conversion ratio verified on the epi wafer, not just the substrate.
- Tot variation (TTV / warp / bow): TTV ≤3 μm, bow ≤10 μm, warp ≤15 μm for 150mm; 200mm tolerances are typically 2–3× looser today — a real process-window cost for the fab.
- Polytype inclusions and scratch network: require full-surface optical inspection maps (e.g. defect-classified), not sample photos.
- Surface roughness and cleanliness: Ra <0.5 nm on the Si-face, particle counts per SEMI-style epi-ready classification.
150mm vs 200mm: the economics
150mm is the workhorse: mature growth on established PVT reactors, high yield, and the deepest supplier pool — which is exactly why price competition is fierce. Reference bands observed in 2026 trading put device-grade n-type 150mm wafers roughly in the $400–700 range depending on MPD/BPD grade and volume, with qualified Chinese supply consistently undercutting incumbent quotes by 30–50% at comparable incoming specs. The 200mm story is different: wafers command a strong premium (commonly $1,000–1,500 reference range), but die-per-wafer economics only pay off if fab tools, epi reactors and yield learning curves keep pace. Our take: dual-source on 150mm today, qualify 200mm on engineering lots, and avoid locking long-term 200mm pricing before epi-house yield data stabilizes.
The buyer verification protocol
Do not accept datasheets as the contract. A workable incoming protocol for a first article and periodic lots:
- X-ray rocking curve (or equivalent crystallinity mapping) to catch polytype inclusions and low-angle grain boundaries.
- Full-wafer photoluminescence or KOH-etch sampling for dislocation class counts — require maps, not summary numbers.
- Resistivity mapping (contactless, 49+ points) with wafer-level uniformity, not a single average.
- Geometry metrology (TTV/bow/warp/orientation) on 100% of production lots.
- Retain wafers from each lot for cross-lab arbitration; agree the arbitration lab and method in the supply agreement before the first PO.
Risks worth pricing in
Three: (1) batch variance — crystal growth is still a per-boule art, so spec on a per-lot basis with reject/remake clauses; (2) 200mm transition distortion — aggressive 200mm pricing now may quietly relax defect specs, so re-baseline specs per diameter; (3) export-control friction on related SiC items has shifted trade routing, so confirm Incoterms, HS classification and license lead times with your forwarder before committing delivery windows.
Bottom line
For device makers and module houses sourcing today: 150mm n-type 4H-SiC from two qualified suppliers — one incumbent, one Chinese — with contractually bound MPD/BPD/TTV values and the verification protocol above is the cost-optimal configuration in 2026. Treat 200mm as a qualification project, not a procurement default. Price ranges cited are market reference bands as of October 2026 and should be re-quoted against current RFQs before contracting.
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