The substrate is the foundation the entire device is built on, and its quality sets a ceiling that no downstream process can raise. A substrate specification that is written loosely, or verified badly on receipt, shows up months later as device parametrics that cannot be explained. This guide covers how to match a substrate to an application, which parameters to write into the specification, and how to inspect on arrival when sourcing from China.
Matching substrate to application
Silicon and silicon on insulator
Single crystal silicon in 6, 8 and 12 inch diameters remains the base for logic, memory and most analog devices. Silicon on insulator, SOI, adds a buried oxide layer that reduces parasitic capacitance and leakage, and it is used for low power logic and for RF switches where substrate isolation matters.
Sapphire
Sapphire is the workhorse substrate for LED epitaxy and for RF filter devices, chosen for its optical transparency, high hardness and electrical insulation. Both C-plane and off-axis orientations are supplied depending on the epitaxial process.
Piezoelectric substrates for filters
Lithium niobate and lithium tantalate are the standard substrates for surface acoustic wave and bulk acoustic wave filters, and their use is expanding into photonics where their electro-optic properties are exploited. Substrate orientation and poling state are critical here, because they fix the piezoelectric response.
Wide and ultra wide bandgap substrates
Silicon carbide is established for power devices. Gallium oxide is an emerging ultra wide bandgap material for high voltage power, offering lower cost potential than SiC if its thermal management challenges can be handled. Gallium nitride is grown on silicon, silicon carbide or sapphire depending on the voltage and cost target.
Compound semiconductor substrates for photonics and RF
Indium phosphide underpins long wavelength optical communication and high frequency electronics. Germanium serves infrared optics and as a channel material option. Quartz and fused silica substrates are used for optical components, photomasks and MEMS.
The specification axes that determine yield
1. Size, orientation and off-axis angle
State the diameter, the primary and secondary flat or notch orientation, the crystallographic plane, and, where relevant, the off-axis angle with its tolerance. For epitaxy, an off-axis angle that is outside tolerance changes growth morphology and cannot be corrected downstream.
2. Surface geometry
Total thickness variation, TTV, bow, warp and local thickness variation describe how flat the wafer actually is. These determine whether a lithography step across the full wafer can hold focus, and they become more demanding as device features shrink.
3. Surface finish and roughness
Specify the polishing route and the surface roughness in the appropriate band. Double side polished wafers give parallel surfaces and tighter geometry. Chemical mechanical polished surfaces give the lowest roughness for epitaxy. Roughness targets for epi-ready surfaces are typically at the sub nanometre root mean square level, and the measurement method and scan area should both be named.
4. Defect density
Different substrate families have different defect limits. Compound substrates are specified by etch pit density or dislocation density, silicon carbide substrates by micropipe density and basal plane dislocation density, and all substrates by scratch, haze and included particle counts. These are the parameters that most directly translate into device yield and must be specified with the measurement method.
5. Electrical parameters
Resistivity, doping type and carrier concentration define the substrate’s role in the device. For semi-insulating substrates used in RF, the resistivity is specified in the very high range and measured by a defined method. For conductive substrates, specify doping type and both resistivity and carrier concentration ranges.
6. Epi readiness
If the substrate will receive an epitaxial layer, it should be specified as epi-ready, which carries additional requirements on surface roughness, defect level, residual contamination and packaging cleanliness. Confirm whether the supplier’s definition of epi-ready matches your epitaxy process.
Incoming inspection checklist
- Verify lot identity and packaging seal before opening, and handle only in the appropriate cleanroom class.
- Measure geometry on a sample from each lot: thickness, TTV, bow and warp against the specification.
- Measure surface roughness by the agreed method on a sample, and check for haze and light point defects under the specified illumination.
- Inspect for scratches and edge chips at the magnifications defined in the specification, since edge damage propagates into epitaxy and lithography.
- Check resistivity and carrier concentration by the agreed method, non contact where possible to preserve the wafer.
- Confirm defect density data from the supplier’s own inspection, and periodically verify it against an independent measurement.
Packaging and cleanliness
A substrate that meets its specification at the supplier can still arrive out of specification if packaging is wrong. Require a defined cleanroom class for packing, vacuum sealed or nitrogen purged inner packaging for epi-ready surfaces, and a rigid shipping box or FOUP compatible with your handling equipment for larger diameters. Confirm that the shipment includes the lot documentation, and that the package can be opened without particle generation at the point of use.
Common sourcing mistakes
- Specifying diameter and orientation but not TTV, bow and warp, then discovering a lithography focus problem.
- Treating epi-ready as a marketing term rather than a set of measurable requirements.
- Accepting defect density figures without knowing the measurement method, since different methods give very different numbers.
- Ignoring edge quality, which is a leading cause of downstream breakage and defect generation.
- Not matching the shipping container to the fab handling equipment, then re handling the wafers and adding particles.
Sourcing substrates from Hunan and China
China has developed a broad substrate industry spanning silicon, sapphire, silicon carbide and compound semiconductors, supported by growing domestic demand and by materials research capacity. Hunan hosts semiconductor materials suppliers serving both domestic device makers and export customers, within the province advanced materials industrial base. LiiFoo maintains verified supplier profiles in the cutting-edge materials cluster with documented substrate capability and certification.
For specification matched quotes, sample wafers with inspection data or a supplier qualification shortlist, see the cluster above or contact our sourcing team.
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