Silicon Carbide (SiC) Substrate Procurement Guide: Wafer Grades, 6-inch Epitaxial Wafers and SiC vs IGBT Trade-offs

For power-electronics buyers, the silicon carbide substrate is the foundation

A silicon carbide (SiC) substrate is no longer a research curiosity—it is the foundation of every SiC MOSFET, diode and power module shipping into EVs, solar inverters, fast chargers and industrial drives. If you are building an RFQ, qualifying a second source, or deciding whether to migrate a design from silicon IGBTs to SiC, this guide consolidates the specifications, grades and trade-offs you need to specify and source with confidence in 2026.

Why the substrate sits at the center of SiC procurement

A SiC device is built in layers: a high-quality 4H-SiC single-crystal substrate, a homoepitaxial drift layer grown on top, and the device structures fabricated in that epilayer. The substrate sets the ceiling for defect density, yield and long-term reliability. A wafer with high micropipe density or poor crystal orientation will undermine even a perfect epitaxy step. That is why substrate procurement deserves the same rigor you apply to the device itself.

Substrate grades and the specifications buyers must lock

When you request a quote, do not stop at “4H-SiC, 6-inch.” Pin down the parameters that actually move yield:

• Polytype and orientation: 4H-SiC is the production standard for power devices; (0001) semi-insulating or conductive orientations are selected by device type. Off-axis cut (typically 4° toward [11-20]) is standard for epitaxy.
• Resistive grade: n-type (doped with nitrogen) for conductive substrates, or high-resistivity for RF. Specify resistivity range, not just “conductive.”
• Defect metrics: micropipe density (MPD) should be near zero for power grades; target basal plane dislocation (BPD) and threading screw dislocation (TSD) limits explicitly.
• Geometry: thickness, total thickness variation (TTV), bow, warp and surface roughness (RA). Tighter TTV and bow directly improve epitaxy uniformity.
• Wafer size: 150 mm (6-inch) is now the mainstream production diameter, with 200 mm ramping. Specify diameter and edge profile.

A precise spec sheet shortens supplier qualification and prevents “samples pass, production fails” surprises.

6-inch SiC epitaxial wafers: what the epilayer spec must say

Most buyers do not buy a bare substrate alone—they buy a 6-inch SiC epitaxial wafer with a defined drift layer. The epilayer, not the substrate, defines the blocking voltage and on-resistance of the final device. Lock these:

• Epilayer thickness: matched to target voltage class (e.g., ~10–15 µm for 650–1200 V, thicker for 1700 V+).
• Doping concentration and uniformity: specify average doping and across-wafer uniformity (CV%); tighter uniformity means predictable V_BR and R_DS(on).
• Defect control: epitaxial defects such as carrot, triangle and down-fall defects cap device yield. Set a classified defect map and acceptable counts.
• Surface quality: RMS roughness in the sub-nm range; particulates per wafer limit.

When comparing Chinese, European and Japanese epitaxy houses, request a full mapping report, not just a COA, and validate by a trial lot before volume commitment.

SiC vs Silicon IGBT: the procurement trade-off in 2026

The single most common buying question is whether to stay on silicon IGBTs or switch to SiC. Frame it as total cost of ownership, not device price:

• Efficiency: SiC cuts switching and conduction losses dramatically, especially at high frequency. In an EV inverter or solar string inverter this recovers 1–2% system efficiency, reducing cooling mass and battery/panel cost.
• Cost: SiC dies still cost more per amp, but the system-level bill often closes once you subtract heatsink, filter and magnetics savings. At high switching frequencies the gap narrows fastest.
• Reliability and thermal: SiC runs cooler and tolerates higher junction temperature (175–200 °C), extending life in automotive and industrial duty.
• When IGBT still wins: low-frequency, cost-sensitive, thermally forgiving applications where the SiC premium cannot be recovered in system savings.

For procurement, the right answer is per-application: qualify SiC for efficiency-critical, high-frequency designs; keep IGBTs where the business case does not support the premium.

RFQ and sourcing checklist

Before you issue an RFQ, compile: target voltage/class, wafer diameter, substrate grade, epilayer thickness and doping, defect limits, volume and delivery cadence, COA/mapping requirements, and a qualification lot. Ask suppliers for traceable origin, yield data and a failure-mode history. Dual-source early—SiC capacity is tightening as EV demand scales.

Conclusion

Procuring SiC is procuring the substrate-and-epilayer system, not a standalone chip. Lock the substrate grade, specify the 6-inch epitaxial wafer precisely, and decide SiC vs IGBT on system total cost. Do that, and your 2026 sourcing will be faster, cheaper and far less risky.