Silicon carbide (SiC) substrates are the foundation of the third-generation semiconductor value chain, directly determining epitaxy quality, device yield, and final cost. In 2026, with 8-inch production lines ramping up and substrate prices continuing to fall, the selection logic is shifting. This guide covers the key decisions from three angles: substrate type, wafer size, and application fit.
1. Two Fundamentally Different Types: Conductive vs Semi-Insulating
- Conductive (N-type) substrates: resistivity around 0.015–0.028 Ω·cm, used for SiC power devices (MOSFETs, Schottky diodes). Main applications: EV traction inverters, solar inverters, fast chargers, and industrial power supplies. They account for over 80% of total demand.
- Semi-insulating substrates: resistivity ≥1×10&sup5; Ω·cm (high-purity grades reach 10&sup9; and above), used for GaN-on-SiC RF devices in 5G base station power amplifiers, satellite communications, and radar. They demand far stricter micropipe and impurity control and carry a significant price premium.
2. 6-Inch or 8-Inch? The 2026 Cost Crossover
An 8-inch (200 mm) wafer offers roughly 1.8× the usable area of a 6-inch wafer with lower edge loss, cutting theoretical per-die cost by 20–35%. But three practical conditions matter:
- Fab readiness: confirm your downstream fab has qualified 8-inch epitaxy and process flows. Leading IDMs (STMicroelectronics, Infineon, onsemi) and major Chinese device makers now run 8-inch lines, but some foundry capacity remains 6-inch centric.
- Supply stability: 8-inch yield ramp is still in progress. Bow/warp control varies more between batches than on mature 6-inch products, so request batch consistency data before signing.
- Pricing dynamics: 6-inch conductive substrates have entered a highly competitive price range and remain the best value for small-to-mid volume projects; 8-inch suits programs with firm high-volume ramp plans and long-term agreements.
3. Quality Parameters That Matter More Than Price
- Micropipe density (MPD): mainstream production now achieves ≤0.5 /cm²; for power devices, specify ≤0.2 /cm².
- Dislocation density: threading screw dislocations (TSD) and basal plane dislocations (BPD). BPDs cause bipolar degradation and device drift — automotive programs should contractually cap BPD levels.
- Bow, warp and TTV: these affect epitaxial uniformity and lithography alignment. For 8-inch, target bow ≤25 μm and TTV ≤5 μm.
- Surface roughness: post-CMP Ra typically ≤0.2 nm, which directly determines epi-layer defect density.
4. Matching Substrates to Applications
- EV traction inverters (800V platforms): prioritize 8-inch conductive substrates with 2–3 year supply agreements; focus on BPD limits and batch consistency.
- Solar and energy storage inverters: 6-inch conductive remains mainstream; high cost sensitivity favors a multi-supplier strategy.
- RF power amplifiers (5G/satellite): choose high-purity semi-insulating grades; verify resistivity uniformity and thermal conductivity data.
- R&D and small-batch tape-outs: 6-inch offers better availability, shorter lead times, and mature process databases.
5. 2026 Procurement Takeaways
In short: commit to 8-inch with long-term agreements for high-volume automotive programs, keep leveraging the 6-inch cost advantage for smaller or cost-sensitive projects, and run a separate semi-insulating qualification track for RF work. Whichever route you choose, write micropipe density, BPD, bow/warp acceptance criteria and batch traceability into the contract — shifting quality risk management upstream into procurement.
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