Bottom line for buyers: GaN is no longer a “new material” purchase — it is a device purchase with material-level risk. The three things that decide whether your GaN program succeeds are (1) the substrate route you buy into, (2) whether you contractually lock dynamic RDS(on) rather than the datasheet headline number, and (3) whether you understand that GaN has no standard pinout, so your second source is a design decision made at RFQ time, not a purchasing decision made later. Everything else — price, freight, duty — is arithmetic.
1. What you are actually buying
A GaN power transistor is a lateral HEMT: current flows sideways through a two-dimensional electron gas (2DEG) formed at an AlGaN/GaN interface. This is structurally different from a silicon MOSFET or a SiC MOSFET, and the differences drive the whole procurement conversation:
- No intrinsic body diode. Reverse recovery charge (Qrr) is effectively zero. This is the single biggest reason GaN wins in hard-switching bridge topologies and why it enables MHz-class operation.
- Very low output charge (QOSS) and gate charge (QG). Switching loss collapses; magnetics shrink; power density rises. This is what makes a 140 W charger fit in a palm.
- Lateral geometry = surface-sensitive device. Charge trapping at the surface and buffer causes on-resistance to rise transiently under high-voltage switching stress. This effect has no equivalent in a silicon MOSFET datasheet, and it is where most disappointed GaN buyers get hurt.
- Narrow gate window (p-GaN gate types). Typical absolute-maximum VGS is around 6–7 V versus 20 V for silicon. Gate drive design tolerance is tight, and a sloppy layout destroys parts in the field, not on the bench.
2. Substrate route: the decision that sets your cost and your ceiling
| Route |
Typical voltage / use |
Why buyers choose it |
Watch-outs |
| GaN-on-Si |
100 V, 200 V, 650 V — chargers, adapters, server PSU, micro-inverter, 48 V DC-DC |
Lowest cost per amp; runs on 6-inch and 8-inch silicon lines, so capacity is real and scalable |
Silicon substrate thermal conductivity (~150 W/m·K) limits continuous power; buffer-layer engineering quality varies widely between suppliers |
| GaN-on-SiC |
RF power amplifiers, 5G/6G base stations, radar, satcom |
SiC substrate conducts heat ~3x better (~370–490 W/m·K); highest power density and RF linearity |
Substrate cost dominates BOM; export-control exposure is highest here; lead times long |
| GaN-on-sapphire |
Low-power consumer chargers |
Cheapest substrate; adequate for low-duty adapters |
Poor thermal path (~35 W/m·K). Do not accept for anything with sustained load or a small enclosure |
| GaN-on-GaN (bulk) |
Vertical devices, lasers, niche high-current |
Best crystal quality, vertical current path |
Substrate supply is thin and expensive; treat as R&D, not production sourcing, in 2026 |
Practical rule: if the application is an AC-DC converter under ~3 kW, specify GaN-on-Si and negotiate on price. If the application is RF, you are buying GaN-on-SiC and negotiating on lead time and licence paperwork, not price.
3. Device architecture: cascode vs. true enhancement mode
Both are sold as “normally-off GaN.” They behave differently and they are not interchangeable in your gate drive.
- Cascode — a depletion-mode GaN HEMT stacked with a low-voltage silicon MOSFET in one package. You drive it like a silicon MOSFET (0–10/12 V gate), which makes it the low-risk retrofit for existing designs. Cost: a small but non-zero Qrr from the Si device, extra package parasitics, and a slightly higher RDS(on) floor.
- p-GaN gate (e-mode) — a genuinely enhancement-mode single die. Best figures of merit and the highest achievable switching frequency, but gate drive must respect a ~5–6 V nominal / ~6–7 V absolute-max window, and gate current (not just voltage) needs managing.
- Integrated GaN power IC — driver, level shift, protection and sometimes sensing co-integrated with the HEMT. Fewer parts, drastically fewer layout mistakes, faster time-to-market. The trade: you are locked to one vendor’s part, and there is no drop-in alternate. Buy this when schedule risk outweighs supply risk.
4. The spec sheet you must send with your RFQ
A GaN RFQ that only states voltage, current and package will get you quotes you cannot compare. Lock these fields:
- VDS rating and transient limit — 650 V devices are commonly rated to a higher transient VDS; ask for the specified transient value and its duration, not marketing language.
- RDS(on) at 25 °C and at TJ = 125 °C. GaN’s temperature coefficient is typically 1.7–2.3x from 25 °C to 125 °C. If a supplier only quotes 25 °C, your thermal design is built on a number you will never see in operation.
- Dynamic RDS(on) data, measured under your switching conditions. Request characterisation aligned to JEDEC JEP180 (the industry guideline for dynamic on-resistance measurement of GaN power devices), at rated VDS, at 125 °C, at your switching frequency. Ask for the ratio RDS(on),dyn/RDS(on),static. A ratio near 1.1–1.3 is a mature process; a supplier who cannot produce the data at all has told you something important.
- QG, QOSS, EOSS, COSS(tr), CISS — QOSS and EOSS drive soft-switching loss and are frequently under-specified.
- Gate: VGS nominal, absolute max, threshold VTH and its distribution. Ask for the VTH spread across lots, not just the typical.
- Thermal: Rth(j-c) and Rth(j-a), cooling side (top-side cooled vs. bottom-side). Top-side-cooled packages change your entire PCB and heatsink design — decide before layout.
- Package and isolation — PQFN, DFN, TOLL, embedded/chip-scale. For lateral GaN, confirm creepage and clearance between drain and source pads against your end-product safety standard (e.g. IEC 62368-1 for IT/AV equipment).
- Reliability qualification evidence — HTRB, HTGB, H3TRB, temperature cycling, IOL, and for automotive, AEC-Q101 plus PPAP. Ask specifically about switching-stress reliability (JEDEC JEP173 addresses this class of testing); DC-only qualification data is insufficient for a hard-switching converter.
- MSL rating, dry-pack condition, reflow profile, tape-and-reel format, MOQ.
- Lot traceability and COA content — wafer lot, assembly lot, date code, and the electrical parameters actually measured at final test.
5. The three risks that are specific to sourcing GaN from China
5.1 Export licensing on gallium items
Since August 2023 China has applied export licence control to gallium-related items, and gallium nitride appears among the controlled categories. In practice, packaged finished devices and modules are treated very differently from gallium metal, GaN substrates and epitaxial wafers. If you are buying finished transistors or power ICs, this usually does not bite. If you are buying GaN epi wafers, substrates or bare die, assume a licence step and build weeks of lead time into your schedule. Ask your exporter, in writing and before the PO: which HS code will be declared, is a licence required, has it been granted, and what is the current approval turnaround. Control lists change — verify current status rather than relying on any article, including this one.
5.2 Tariff and classification exposure
Discrete GaN transistors and GaN power ICs classify differently (transistor headings vs. integrated-circuit headings), and the duty and trade-remedy treatment can differ meaningfully as a result — particularly for US importers, where semiconductor tariff lines have been revised upward in recent rounds. Get the classification confirmed by your customs broker on a sample invoice before you commit to volume pricing, and make sure your supplier’s declared HS code matches. A landed-cost model built on the wrong heading is not a model, it is a surprise.
5.3 No standard pinout — second sourcing is a design task
Unlike silicon MOSFETs, GaN devices from different vendors are rarely pin-compatible, and integrated GaN power ICs never are. This is the most common structural mistake in GaN procurement: the team designs in one vendor’s part, then discovers at ramp that there is no alternate. Mitigations, in order of effectiveness: design to a widely-supported industry footprint (TOLL, standard PQFN sizes) where performance allows; qualify two suppliers on the same footprint during development, not after; and if you must use a single-source integrated IC, negotiate a buffer-stock or last-time-buy clause at the same time as price.
6. Landed-cost model
Build the model in this order and do not skip lines 4–7, which is where GaN programs quietly lose their cost advantage:
- FOB unit price at your annual volume (ask for a price break table: 10k / 100k / 500k / 1M)
- Freight — semiconductors ship air; small weight, non-trivial cost per shipment, so consolidate
- Duty and trade remedies, on the confirmed HS code
- Customs brokerage, ESD/MSL-compliant packaging, and dry-pack handling
- Incoming inspection cost (see section 7) and expected fallout rate
- Inventory carrying cost of the safety stock your single-source risk forces you to hold
- System-level offset — GaN’s honest cost case is at system level, not device level: smaller magnetics, smaller heatsink, fewer capacitors, higher-efficiency rating tier. Quantify the BOM you delete. If you compare GaN to silicon on device price alone, GaN always loses and you have measured the wrong thing.
On price direction in 2026: 8-inch GaN-on-Si capacity is now in genuine volume production, which has compressed 650 V die cost and moved the competitive battleground from “can you supply” to “can you prove dynamic RDS(on) and reliability.” Treat any quote that is dramatically below the market band as a data-request trigger, not a win.
7. Incoming inspection that actually catches GaN problems
- Curve tracer / parametric: RDS(on) at specified VGS, VTH, IDSS and IGSS leakage. Track VTH distribution lot over lot — drift is an early warning of a process change you were not told about.
- Double-pulse test (DPT): the only realistic way to verify switching energy and dynamic on-resistance behaviour in your own topology. Make DPT results part of first-article approval.
- Thermal imaging under load at rated power, in your enclosure, not on an open bench.
- Package/board-level: X-ray or CSAM on a sample for voiding under the thermal pad; confirm MSL floor life was respected in transit.
8. Design guardrails to write into the specification
These are the failure modes that generate field returns and then get blamed on the supplier:
- Loop inductance. High-frequency GaN needs a power loop typically under a few nH. Long loops turn fast dv/dt into VDS overshoot that exceeds the transient rating.
- Kelvin source connection to decouple gate drive from common-source inductance.
- Gate loop protection — with a ~6 V absolute maximum, ringing that a silicon design would tolerate is destructive here. Series gate resistance, tight return path, and clamping where appropriate.
- Dead-time management — no body diode means no forgiving reverse conduction path; shoot-through margins must be verified, not assumed.
9. A workable 2026 sequence
- Weeks 1–2: fix application, topology, frequency and thermal budget. Choose substrate route (section 2) and architecture (section 3).
- Weeks 2–4: issue the RFQ with the full spec sheet from section 4. Reject quotes missing dynamic RDS(on) and 125 °C data.
- Weeks 4–8: samples from at least two suppliers on the same footprint. Run DPT plus thermal validation in the real enclosure.
- Weeks 8–12: confirm HS code and licence status in writing; run a small paid trial shipment to validate documents, MSL packaging and broker handling before volume.
- Ongoing: lot-to-lot parametric trending, and a contractual change-notification clause covering wafer fab, epi supplier, buffer structure and assembly site. In GaN, a “minor” epi change is not minor.
Standards and control lists referenced here (JEP180, JEP173, AEC-Q101, IEC 62368-1, gallium export controls, tariff classifications) are cited as procurement checkpoints. Confirm current revisions and current legal status with the issuing body, your customs broker and your supplier before contracting.